riscv/rocket-chip
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Pipeline D$ exception response into s2

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This commit is contained in:
Andrew Waterman
2017-04-14 23:57:32 -07:00
committed by Andrew Waterman
parent 657f4d4e0c
commit 6de6f38894
7 changed files with 21 additions and 27 deletions
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6
src/main/scala/rocket/NBDcache.scala
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@ -677,12 +677,12 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.cpu.req.ready := Bool(true)
val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
val s1_req = Reg(io.cpu.req.bits)
val s1_valid_masked = s1_valid && !io.cpu.s1_kill && !io.cpu.xcpt.asUInt.orR
val s1_valid_masked = s1_valid && !io.cpu.s1_kill
val s1_replay = Reg(init=Bool(false))
val s1_clk_en = Reg(Bool())
val s1_sfence = s1_req.cmd === M_SFENCE
val s2_valid = Reg(next=s1_valid_masked && !s1_sfence, init=Bool(false))
val s2_valid = Reg(next=s1_valid_masked && !s1_sfence, init=Bool(false)) && !io.cpu.s2_xcpt.asUInt.orR
val s2_req = Reg(io.cpu.req.bits)
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd =/= M_FLUSH_ALL
val s2_recycle = Wire(Bool())
@ -699,7 +699,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> dtlb.io.ptw
io.cpu.xcpt := dtlb.io.resp
io.cpu.s2_xcpt := RegEnable(Mux(dtlb.io.req.valid && !dtlb.io.resp.miss, dtlb.io.resp, 0.U.asTypeOf(dtlb.io.resp)), s1_clk_en)
dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
dtlb.io.req.bits.sfence.valid := s1_sfence
dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)