riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2 Crossing: cut the crossing between clock domains

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-09-29 17:32:18 -07:00
parent 20f42a8762
commit 6d8c965f04
2 changed files with 87 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/uncore/tilelink2/Fuzzer.scala
View File

@ -224,8 +224,8 @@ class TLFuzzRAM extends LazyModule
xbar2.node := TLAtomicAutomata()(model.node)
ram2.node := TLFragmenter(16, 256)(xbar2.node)
xbar.node := TLWidthWidget(16)(TLHintHandler()(xbar2.node))
cross.node := TLFragmenter(4, 256)(TLBuffer()(xbar.node))
val monitor = (ram.node := cross.node)
cross.nodeIn := TLFragmenter(4, 256)(TLBuffer()(xbar.node))
val monitor = (ram.node := cross.nodeOut)
gpio.node := TLFragmenter(4, 32)(TLBuffer()(xbar.node))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {