riscv/rocket-chip
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clean up acquire alloc in hub

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This commit is contained in:
Henry Cook 2015-03-17 00:23:11 -07:00
parent 3f070eee1f
commit 6d565d22e3
2 changed files with 15 additions and 12 deletions
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24
uncore/src/main/scala/broadcast.scala
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@ -48,25 +48,29 @@ class L2BroadcastHub(bankId: Int) extends ManagerCoherenceAgent
when (sdq_enq) { sdq(sdq_alloc_id) := io.iacq().data } when (sdq_enq) { sdq(sdq_alloc_id) := io.iacq().data }
// Handle acquire transaction initiation // Handle acquire transaction initiation
val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
val trackerAcquireIOs = trackerList.map(_.io.inner.acquire) val trackerAcquireIOs = trackerList.map(_.io.inner.acquire)
val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
alloc_arb.io.out.ready := Bool(true)
trackerAcquireIOs.zip(alloc_arb.io.in).foreach {
case(tracker, arb) => arb.valid := tracker.ready
}
val alloc_idx = Vec(alloc_arb.io.in.map(_.ready)).lastIndexWhere{b: Bool => b}
val acquireMatchList = trackerList.map(_.io.has_acquire_match) val acquireMatchList = trackerList.map(_.io.has_acquire_match)
val any_acquire_matches = acquireMatchList.reduce(_||_) val any_acquire_matches = acquireMatchList.reduce(_||_)
val alloc_idx = Vec(alloc_arb.io.in.map(_.ready)).lastIndexWhere{b: Bool => b}
val match_idx = Vec(acquireMatchList).indexWhere{b: Bool => b} val match_idx = Vec(acquireMatchList).indexWhere{b: Bool => b}
val acquire_idx = Mux(any_acquire_matches, match_idx, alloc_idx) val acquire_idx = Mux(any_acquire_matches, match_idx, alloc_idx)
trackerAcquireIOs.zip(alloc_arb.io.in).zipWithIndex.foreach { val block_acquires = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
case((tracker, arb), i) => io.inner.acquire.ready := trackerAcquireIOs.map(_.ready).reduce(_||_) && !block_acquires && sdq_rdy
arb.valid := tracker.ready trackerAcquireIOs.zipWithIndex.foreach {
case(tracker, i) =>
tracker.bits := io.inner.acquire.bits tracker.bits := io.inner.acquire.bits
tracker.bits.payload.data := tracker.bits.payload.data :=
DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
tracker.valid := arb.ready && (acquire_idx === UInt(i)) tracker.valid := io.inner.acquire.valid && !block_acquires && (acquire_idx === UInt(i))
} }
val block_acquires = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
io.inner.acquire.ready := trackerAcquireIOs.map(_.ready).reduce(_||_) &&
sdq_rdy && !block_acquires
alloc_arb.io.out.ready := io.inner.acquire.valid && sdq_rdy && !block_acquires
// Queue to store impending Voluntary Release data // Queue to store impending Voluntary Release data
val voluntary = io.irel().isVoluntary() val voluntary = io.irel().isVoluntary()

3
uncore/src/main/scala/cache.scala
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@ -376,8 +376,7 @@ class TSHRFile(bankId: Int) extends L2HellaCacheModule
val alloc_arb = Module(new Arbiter(Bool(), trackerList.size)) val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
alloc_arb.io.out.ready := Bool(true) alloc_arb.io.out.ready := Bool(true)
trackerAcquireIOs.zip(alloc_arb.io.in).foreach { trackerAcquireIOs.zip(alloc_arb.io.in).foreach {
case(tracker, arb) => case(tracker, arb) => arb.valid := tracker.ready
arb.valid := tracker.ready
} }
val alloc_idx = Vec(alloc_arb.io.in.map(_.ready)).lastIndexWhere{b: Bool => b} val alloc_idx = Vec(alloc_arb.io.in.map(_.ready)).lastIndexWhere{b: Bool => b}