Update readme to reflect config name changes (#871)

also update list of files expected to be seen in generated-src

README.md

@@ -283,26 +283,23 @@ Or call out individual assembly tests or benchmarks:
     $ make output/rv64ui-p-add.vcd
 
 Now take a look in the emulator/generated-src directory. You will find
-Chisel generated C++ code.
+Chisel generated verilog code and its associated C++ code generated by
+verilator.
 
     $ ls $ROCKETCHIP/emulator/generated-src
-    Top.DefaultConfig-0.cpp
-    Top.DefaultConfig-0.o
-    Top.DefaultConfig-1.cpp
-    Top.DefaultConfig-1.o
-    Top.DefaultConfig-2.cpp
-    Top.DefaultConfig-2.o
-    Top.DefaultConfig-3.cpp
-    Top.DefaultConfig-3.o
-    Top.DefaultConfig-4.cpp
-    Top.DefaultConfig-4.o
-    Top.DefaultConfig-5.cpp
-    Top.DefaultConfig-5.o
-    Top.DefaultConfig.cpp
-    Top.DefaultConfig.h
-    emulator.h
-    emulator_api.h
-    emulator_mod.h
+    DefaultConfig.dts
+    DefaultConfig.graphml
+    DefaultConfig.json
+    DefaultConfig.memmap.json
+    freechips.rocketchip.chip.DefaultConfig
+    freechips.rocketchip.chip.DefaultConfig.d
+    freechips.rocketchip.chip.DefaultConfig.fir
+    freechips.rocketchip.chip.DefaultConfig.v
+    $ ls $ROCKETCHIP/emulator/generated-src/freechips.rocketchip.chip.DefaultConfig
+    VTestHarness__1.cpp
+    VTestHarness__2.cpp
+    VTestHarness__3.cpp
+    ...
 
 Also, output of the executed assembly tests and benchmarks can be found
 at emulator/output/\*.out. Each file has a cycle-by-cycle dump of
@@ -359,16 +356,22 @@ Now take a look at vsim/generated-src, and the contents of the
 Top.DefaultConfig.conf file:
 
     $ cd $ROCKETCHIP/vsim/generated-src
-    Top.DefaultConfig.conf
-    Top.DefaultConfig.prm
-    Top.DefaultConfig.v
-    consts.DefaultConfig.vh
+    DefaultConfig.dts
+    DefaultConfig.graphml
+    DefaultConfig.json
+    DefaultConfig.memmap.json
+    freechips.rocketchip.chip.DefaultConfig.behav_srams.v
+    freechips.rocketchip.chip.DefaultConfig.conf
+    freechips.rocketchip.chip.DefaultConfig.d
+    freechips.rocketchip.chip.DefaultConfig.fir
+    freechips.rocketchip.chip.DefaultConfig.v
     $ cat $ROCKETCHIP/vsim/generated-src/*.conf
-    name MetadataArray_tag_arr depth 128 width 84 ports mwrite,read mask_gran 21
-    name ICache_tag_array depth 128 width 38 ports mrw mask_gran 19
-    name DataArray_T6 depth 512 width 128 ports mwrite,read mask_gran 64
-    name HellaFlowQueue_ram depth 32 width 133 ports write,read
-    name ICache_T157 depth 512 width 128 ports rw
+    name data_arrays_0_ext depth 512 width 256 ports mrw mask_gran 8
+    name tag_array_ext depth 64 width 88 ports mrw mask_gran 22
+    name tag_array_0_ext depth 64 width 84 ports mrw mask_gran 21
+    name data_arrays_0_1_ext depth 512 width 128 ports mrw mask_gran 32
+    name mem_ext depth 33554432 width 64 ports mwrite,read mask_gran 8
+    name mem_2_ext depth 512 width 64 ports mwrite,read mask_gran 8
 
 The conf file contains information for all SRAMs instantiated in the
 flow. If you take a close look at the $ROCKETCHIP/Makefrag, you will see
@@ -412,20 +415,20 @@ divider, and reduces the number of TLB entries (all defined in SmallConfig).
 This small configuration is used for the Zybo FPGA board, which has the
 smallest ZYNQ part.
 
-Towards the end, you can also find that ExampleSmallConfig inherits all
+Towards the end, you can also find that DefaultSmallConfig inherits all
 parameters from BaseConfig but overrides the same parameters of
-SmallConfig.
+WithNSmallCores.
 
 Now take a look at vsim/Makefile. Search for the CONFIG variable.
 By default, it is set to DefaultConfig.  You can also change the
 CONFIG variable on the make command line:
 
     $ cd $ROCKETCHIP/vsim
-    $ make -jN CONFIG=ExampleSmallConfig run-asm-tests
+    $ make -jN CONFIG=DefaultSmallConfig run-asm-tests
 
 Or, even by defining CONFIG as an environment variable:
 
-    $ export CONFIG=ExampleSmallConfig
+    $ export CONFIG=DefaultSmallConfig
     $ make -jN run-asm-tests
 
 This parameterization is one of the many strengths of processor