diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 9ec91845..294e4052 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -4,53 +4,6 @@ package constants
 import Chisel._
 import scala.math._
 
-abstract trait MulticoreConstants {
-  val NTILES: Int
-  val TILE_ID_BITS = log2Up(NTILES)+1
-}
-
-abstract trait CoherenceConfigConstants {
-  val ENABLE_SHARING: Boolean
-  val ENABLE_CLEAN_EXCLUSIVE: Boolean
-}
-
-trait UncoreConstants {
-  val NGLOBAL_XACTS = 8
-  val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS)
-}
-
-trait TileLinkTypeConstants {
-  val X_INIT_TYPE_MAX_BITS = 2
-  val X_REP_TYPE_MAX_BITS = 3
-  val P_REQ_TYPE_MAX_BITS = 2
-  val P_REP_TYPE_MAX_BITS = 3
-}
-
-trait TileLinkSizeConstants extends 
-  RocketDcacheConstants with 
-  TileLinkTypeConstants
-{
-  val TILE_XACT_ID_BITS = log2Up(NMSHR)+3
-  val X_INIT_WRITE_MASK_BITS = OFFSET_BITS
-  val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS)
-  val X_INIT_ATOMIC_OP_BITS = 4
-}
-
-trait HTIFConstants {
-  val HTIF_WIDTH = 16
-}
-
-trait MemoryInterfaceConstants extends 
-  HTIFConstants with 
-  UncoreConstants with 
-  TileLinkSizeConstants 
-{
-  val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)
-  val MEM_DATA_BITS = 128
-  val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
-  val MEM_BACKUP_WIDTH = HTIF_WIDTH
-}  
-
 abstract trait TileConfigConstants {
   def HAVE_RVC: Boolean
   def HAVE_FPU: Boolean
@@ -219,25 +172,19 @@ trait InterruptConstants {
   val IRQ_TIMER = 7
 }
  
-trait AddressConstants { 
-  val PADDR_BITS = 40;
-  val VADDR_BITS = 43;
-  val PGIDX_BITS = 13;
-  val PPN_BITS = PADDR_BITS-PGIDX_BITS;
-  val VPN_BITS = VADDR_BITS-PGIDX_BITS;
-  val ASID_BITS = 7;
-  val PERM_BITS = 6;
-}
-
-abstract trait RocketDcacheConstants extends ArbiterConstants with AddressConstants {
+abstract trait RocketDcacheConstants extends ArbiterConstants with uncore.constants.AddressConstants {
   val CPU_DATA_BITS = 64;
   val CPU_TAG_BITS = 9;
   val DCACHE_TAG_BITS = log2Up(DCACHE_PORTS) + CPU_TAG_BITS
   val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
   val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses
+  require(log2Up(NMSHR)+3 <= uncore.Constants.TILE_XACT_ID_BITS)
   val NRPQ = 16; // number of secondary misses
   val NSDQ = 17; // number of secondary stores/AMOs
   val OFFSET_BITS = 6; // log2(cache line size in bytes)
+  require(OFFSET_BITS == log2Up(uncore.Constants.CACHE_DATA_SIZE_IN_BYTES))
+  require(OFFSET_BITS <= uncore.Constants.X_INIT_WRITE_MASK_BITS)
+  require(log2Up(OFFSET_BITS) <= uncore.Constants.X_INIT_SUBWORD_ADDR_BITS)
   val IDX_BITS = 7;
   val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS;
   val NWAYS = 4
diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala
index aaa06dcd..28fdcfad 100644
--- a/rocket/src/main/scala/package.scala
+++ b/rocket/src/main/scala/package.scala
@@ -8,13 +8,13 @@ import scala.math._
 //      package object rocket and remove import Constants._'s from other files
 object Constants extends 
   ScalarOpConstants with
-  MemoryOpConstants with
+  uncore.constants.MemoryOpConstants with
   PCRConstants with 
   InterruptConstants with 
-  AddressConstants with
+  RocketDcacheConstants with
   VectorOpConstants with 
   TLBConstants with 
-  MemoryInterfaceConstants
+  uncore.constants.MemoryInterfaceConstants
 {
   def HAVE_RVC = false
   def HAVE_FPU = true
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index df6f084d..9e051d0e 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -6,7 +6,7 @@ import Constants._
 import uncore._
 import collection.mutable.ArrayBuffer
 
-object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants with rocket.constants.MulticoreConstants {
+object DummyTopLevelConstants extends uncore.constants.CoherenceConfigConstants {
   val NTILES = 1
   val ENABLE_SHARING = true
   val ENABLE_CLEAN_EXCLUSIVE = true
@@ -24,7 +24,8 @@ class Top extends Component
               if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
               else new MICoherence
             }
-  implicit val conf = RocketConfiguration(NTILES, co)
+  implicit val rconf = RocketConfiguration(NTILES, co)
+  implicit val uconf = UncoreConfiguration(NTILES+1, log2Up(NTILES)+1)
 
   val io = new Bundle  {
     val debug   = new ioDebug
@@ -33,7 +34,7 @@ class Top extends Component
   }
 
   val htif = new rocketHTIF(HTIF_WIDTH)
-  val hub = new CoherenceHubBroadcast(NTILES+1, co)
+  val hub = new CoherenceHubBroadcast(co)
   hub.io.tiles(NTILES) <> htif.io.mem
   io.host <> htif.io.host