riscv/rocket-chip
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Use UInt(0), not UInt(width=0), for constant 0

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This commit is contained in:
Andrew Waterman 2015-07-30 23:45:48 -07:00
parent 4c0f996808
commit 6c391e3b37
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/util.scala
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@ -54,7 +54,7 @@ class FlowThroughSerializer[T <: HasTileLinkData](gen: T, n: Int) extends Module
if(n == 1) { if(n == 1) {
io.in <> io.out io.in <> io.out
io.cnt := UInt(width = 0) io.cnt := UInt(0)
io.done := Bool(true) io.done := Bool(true)
} else { } else {
val cnt = Reg(init=UInt(0, width = log2Up(n))) val cnt = Reg(init=UInt(0, width = log2Up(n)))