riscv/rocket-chip
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remove a partial update that makes chisel barf

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chisel regards it as a combinational loop, even though it isn't.
This commit is contained in:
Andrew Waterman 2012-02-13 16:45:29 -08:00
parent c78c738f60
commit 6c2d8a37ae
2 changed files with 5 additions and 5 deletions
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6
rocket/src/main/scala/fpu.scala
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@ -322,6 +322,9 @@ class rocketIntFPUnit extends Component
out_d := rec_d.io.out
exc_d := Bits(0)
when (io.cmd === FCMD_MTFSR || io.cmd === FCMD_MFFSR) {
out_s := io.in(FSR_WIDTH-1,0)
}
when (io.cmd === FCMD_CVT_FMT_W || io.cmd === FCMD_CVT_FMT_WU ||
io.cmd === FCMD_CVT_FMT_L || io.cmd === FCMD_CVT_FMT_LU) {
out_s := i2s.io.out
@ -329,9 +332,6 @@ class rocketIntFPUnit extends Component
out_d := i2d.io.out
exc_d := i2d.io.exceptionFlags
}
when (io.cmd === FCMD_MTFSR || io.cmd === FCMD_MFFSR) {
out_s := Cat(out_s(32,FSR_WIDTH), io.in(FSR_WIDTH-1,0))
}
io.out := Mux(io.single, Cat(Fill(32,UFix(1)), out_s), out_d)
io.exc := Mux(io.single, exc_s, exc_d)

4
rocket/src/main/scala/top.scala
View File

@ -37,9 +37,9 @@ class Top() extends Component {
object top_main {
def main(args: Array[String]) = {
// Can turn off --debug and --vcd when done with debugging to improve emulator performance
val cpu_args = args ++ Array("--target-dir", "generated-src","--debug","--vcd");
// val cpu_args = args ++ Array("--target-dir", "generated-src","--debug","--vcd");
// val cpu_args = args ++ Array("--target-dir", "generated-src", "--debug");
// val cpu_args = args ++ Array("--target-dir", "generated-src");
val cpu_args = args ++ Array("--target-dir", "generated-src");
// Set variables based off of command flags
// for(a <- args) {
// a match {