riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Turn on the inferRW Firrtl pass

Browse Source 
Without this, all of the memories wind up as two-ported.
This commit is contained in:
Ben Keller 2016-09-07 15:27:26 -07:00
parent 7a6f155b2a
commit 6be569be9f
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
vsim/Makefrag-verilog
View File

@ -11,7 +11,7 @@ $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)
$(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR) $(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@) mkdir -p $(dir $@)
$(FIRRTL) -i $< -o $@ -X verilog --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf $(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
cd $(generated_dir) && \ cd $(generated_dir) && \