From 6bc9c9fc6ca0c41606e45742dea70fbd0619c073 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 19 Oct 2017 18:51:22 -0700
Subject: [PATCH] coreplex: add a crossing wrapper to generalize the island
 pattern

---
 src/main/scala/coreplex/CrossingWrapper.scala | 51 +++++++++++++++++++
 src/main/scala/coreplex/package.scala         | 11 ++++
 2 files changed, 62 insertions(+)
 create mode 100644 src/main/scala/coreplex/CrossingWrapper.scala
 create mode 100644 src/main/scala/coreplex/package.scala

diff --git a/src/main/scala/coreplex/CrossingWrapper.scala b/src/main/scala/coreplex/CrossingWrapper.scala
new file mode 100644
index 00000000..d6508a3f
--- /dev/null
+++ b/src/main/scala/coreplex/CrossingWrapper.scala
@@ -0,0 +1,51 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.coreplex
+
+import Chisel._
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+trait HasCrossingHelper extends LazyScope
+{
+  this: LazyModule =>
+  val crossing: CoreplexClockCrossing
+  def cross(x: TLCrossableNode, name: String): TLOutwardNode = {
+    val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
+    crossing match {
+      case SynchronousCrossing(params) => {
+        val buffer = this { LazyModule(new TLBuffer(params)) }
+        buffer.suggestName(name + "SynchronousBuffer")
+        buffer.node := x.node
+        buffer.node
+      }
+      case RationalCrossing(direction) => {
+        def sourceGen = LazyModule(new TLRationalCrossingSource)
+        def sinkGen = LazyModule(new TLRationalCrossingSink(direction))
+        val source = if (out) this { sourceGen } else sourceGen
+        val sink = if (out) sinkGen else this { sinkGen }
+        source.suggestName(name + "RationalSource")
+        sink.suggestName(name + "RationalSink")
+        source.node := x.node
+        sink.node := source.node
+        sink.node
+      }
+      case AsynchronousCrossing(depth, sync) => {
+        def sourceGen = this { LazyModule(new TLAsyncCrossingSource(sync)) }
+        def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
+        val source = if (out) this { sourceGen } else sourceGen
+        val sink = if (out) sinkGen else this { sinkGen }
+        source.suggestName(name + "AsynchronousSource")
+        sink.suggestName(name + "AsynchronousSink")
+        source.node := x.node
+        sink.node := source.node
+        sink.node
+      }
+    }
+  }
+  // def cross(x: IntCrossableNode, name: String): IntOutwardNode = { x.node }
+}
+
+class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossingHelper
+
diff --git a/src/main/scala/coreplex/package.scala b/src/main/scala/coreplex/package.scala
new file mode 100644
index 00000000..a93eef0c
--- /dev/null
+++ b/src/main/scala/coreplex/package.scala
@@ -0,0 +1,11 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip
+
+import freechips.rocketchip.tilelink._
+
+package object coreplex
+{
+  implicit class TLCrossableNode(val node: TLOutwardNode)
+  implicit class IntCrossableNode(val node: IntOutwardNode)
+}