diplomacy: convert all helper objects to return nodes

src/main/scala/amba/ahb/ToTL.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.ahb
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -132,9 +131,5 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
 
 object AHBToTL
 {
-  def apply()(x: AHBOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+  def apply()(implicit p: Parameters) = LazyModule(new AHBToTL).node
-    val tl = LazyModule(new AHBToTL)
-    tl.node :=? x
-    tl.node
-  }
 }

src/main/scala/amba/axi4/AsyncCrossing.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -44,22 +43,12 @@ class AXI4AsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameter
 
 object AXI4AsyncCrossingSource
 {
-  // applied to the AXI4 source node; y.node := AXI4AsyncCrossingSource()(x.node)
+  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSource(sync)).node
-  def apply(sync: Int = 3)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4AsyncOutwardNode = {
-    val source = LazyModule(new AXI4AsyncCrossingSource(sync))
-    source.node :=? x
-    source.node
-  }
 }
 
 object AXI4AsyncCrossingSink
 {
-  // applied to the AXI4 source node; y.node := AXI4AsyncCrossingSink()(x.node)
+  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSink(depth, sync)).node
-  def apply(depth: Int = 8, sync: Int = 3)(x: AXI4AsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val sink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
-    sink.node :=? x
-    sink.node
-  }
 }
 
 @deprecated("AXI4AsyncCrossing is fragile. Use AXI4AsyncCrossingSource and AXI4AsyncCrossingSink", "rocket-chip 1.2")

src/main/scala/amba/axi4/Buffer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -46,18 +45,13 @@ class AXI4Buffer(
 
 object AXI4Buffer
 {
-  // applied to the AXI4 source node; y.node := AXI4Buffer(x.node)
+  def apply()                                  (implicit p: Parameters): AXI4Node = apply(BufferParams.default)
-  def apply()                                  (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(BufferParams.default)(x)
+  def apply(z: BufferParams)                   (implicit p: Parameters): AXI4Node = apply(z, z)
-  def apply(z: BufferParams)                   (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(z, z)(x)
+  def apply(aw: BufferParams, br: BufferParams)(implicit p: Parameters): AXI4Node = apply(aw, aw, br, aw, br)
-  def apply(aw: BufferParams, br: BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br)(x)
   def apply(
     aw: BufferParams,
     w:  BufferParams,
     b:  BufferParams,
     ar: BufferParams,
-    r:  BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
+    r:  BufferParams)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Buffer(aw, w, b, ar, r)).node
-    val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
-    buffer.node :=? x
-    buffer.node
-  }
 }

src/main/scala/amba/axi4/Deinterleaver.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -100,10 +99,5 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
 
 object AXI4Deinterleaver
 {
-  // applied to the AXI4 source node; y.node := AXI4Deinterleaver()(x.node)
+  def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Deinterleaver(maxReadBytes)).node
-  def apply(maxReadBytes: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val deinterleaver = LazyModule(new AXI4Deinterleaver(maxReadBytes))
-    deinterleaver.node :=? x
-    deinterleaver.node
-  }
 }

src/main/scala/amba/axi4/Fragmenter.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -200,10 +199,5 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
 object AXI4Fragmenter
 {
-  // applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node)
+  def apply()(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Fragmenter).node
-  def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val fragmenter = LazyModule(new AXI4Fragmenter)
-    fragmenter.node :=? x
-    fragmenter.node
-  }
 }

src/main/scala/amba/axi4/IdIndexer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -76,10 +75,5 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
 
 object AXI4IdIndexer
 {
-  // applied to the AXI4 source node; y.node := AXI4IdIndexer(idBits)(x.node)
+  def apply(idBits: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4IdIndexer(idBits)).node
-  def apply(idBits: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val indexer = LazyModule(new AXI4IdIndexer(idBits))
-    indexer.node :=? x
-    indexer.node
-  }
 }

src/main/scala/amba/axi4/ToTL.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -161,9 +160,5 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para
 
 object AXI4ToTL
 {
-  def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+  def apply()(implicit p: Parameters) = LazyModule(new AXI4ToTL).node
-    val tl = LazyModule(new AXI4ToTL)
-    tl.node :=? x
-    tl.node
-  }
 }

src/main/scala/amba/axi4/UserYanker.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.UIntToOH1
@@ -92,10 +91,5 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
 
 object AXI4UserYanker
 {
-  // applied to the AXI4 source node; y.node := AXI4UserYanker(idBits, maxFlight)(x.node)
+  def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4UserYanker(capMaxFlight)).node
-  def apply(capMaxFlight: Option[Int] = None)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val yanker = LazyModule(new AXI4UserYanker(capMaxFlight))
-    yanker.node :=? x
-    yanker.node
-  }
 }

src/main/scala/tilelink/AsyncCrossing.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -68,22 +67,12 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters)
 
 object TLAsyncCrossingSource
 {
-  // applied to the TL source node; y.node := TLAsyncCrossingSource()(x.node)
+  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSource(sync)).node
-  def apply(sync: Int = 3)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLAsyncOutwardNode = {
-    val source = LazyModule(new TLAsyncCrossingSource(sync))
-    source.node :=? x
-    source.node
-  }
 }
 
 object TLAsyncCrossingSink
 {
-  // applied to the TL source node; y.node := TLAsyncCrossingSink()(x.node)
+  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSink(depth, sync)).node
-  def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    sink.node :=? x
-    sink.node
-  }
 }
 
 @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2")

src/main/scala/tilelink/AtomicAutomata.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -257,12 +256,8 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
 
 object TLAtomicAutomata
 {
-  // applied to the TL source node; y.node := TLAtomicAutomata(x.node)
+  def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
-  def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough)).node
-    val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
-    atomics.node :=? x
-    atomics.node
-  }
 
   case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
 

src/main/scala/tilelink/Buffer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -57,20 +56,15 @@ class TLBuffer(
 
 object TLBuffer
 {
-  // applied to the TL source node; y.node := TLBuffer(x.node)
+  def apply()                                   (implicit p: Parameters): TLNode = apply(BufferParams.default)
-  def apply()                                   (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(BufferParams.default)(x)
+  def apply(abcde: BufferParams)                (implicit p: Parameters): TLNode = apply(abcde, abcde)
-  def apply(abcde: BufferParams)                (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
+  def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
-  def apply(ace: BufferParams, bd: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
   def apply(
       a: BufferParams,
       b: BufferParams,
       c: BufferParams,
       d: BufferParams,
-      e: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+      e: BufferParams)(implicit p: Parameters): TLNode = LazyModule(new TLBuffer(a, b, c, d, e)).node
-    val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
-    buffer.node :=? x
-    buffer.node
-  }
 
   def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
     val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }

src/main/scala/tilelink/CacheCork.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -122,10 +121,5 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
 
 object TLCacheCork
 {
-  // applied to the TL source node; y.node := TLCacheCork()(x.node)
+  def apply(unsafe: Boolean = false)(implicit p: Parameters): TLNode = LazyModule(new TLCacheCork(unsafe)).node
-  def apply(unsafe: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val cork = LazyModule(new TLCacheCork(unsafe))
-    cork.node :=? x
-    cork.node
-  }
 }

src/main/scala/tilelink/Delayer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 
@@ -73,10 +72,5 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
 
 object TLDelayer
 {
-  // applied to the TL source node; y.node := TLDelayer(0.01)(x.node)
+  def apply(q: Double)(implicit p: Parameters): TLNode = LazyModule(new TLDelayer(q)).node
-  def apply(q: Double)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val delayer = LazyModule(new TLDelayer(q))
-    delayer.node :=? x
-    delayer.node
-  }
 }

src/main/scala/tilelink/FIFOFixer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.max
@@ -114,10 +113,5 @@ object TLFIFOFixer
   val allFIFO:        Policy = m => m.fifoId.isDefined
   val allUncacheable: Policy = m => m.regionType <= UNCACHEABLE
 
-  // applied to the TL source node; y.node := TLFIFOFixer()(x.node)
+  def apply(policy: Policy = all)(implicit p: Parameters): TLNode = LazyModule(new TLFIFOFixer(policy)).node
-  def apply(policy: Policy = all)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val fixer = LazyModule(new TLFIFOFixer(policy))
-    fixer.node :=? x
-    fixer.node
-  }
 }

src/main/scala/tilelink/Filter.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -92,9 +91,5 @@ object TLFilter
   def apply(
     Mfilter: TLManagerParameters => Option[TLManagerParameters] = TLFilter.Midentity,
     Cfilter: TLClientParameters  => Option[TLClientParameters]  = TLFilter.Cidentity
-    )(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    )(implicit p: Parameters): TLNode = LazyModule(new TLFilter(Mfilter, Cfilter)).node
-    val filter = LazyModule(new TLFilter(Mfilter, Cfilter))
-    filter.node := x
-    filter.node
-  }
 }

src/main/scala/tilelink/Fragmenter.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -283,12 +282,8 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
 
 object TLFragmenter
 {
-  // applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4)
+  def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: Boolean = false)(implicit p: Parameters): TLNode =
-  def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck)).node
-    val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck))
-    fragmenter.node :=? x
-    fragmenter.node
-  }
 }
 
 /** Synthesizeable unit tests */

src/main/scala/tilelink/HintHandler.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.min
@@ -92,12 +91,8 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
 
 object TLHintHandler
 {
-  // applied to the TL source node; y.node := TLHintHandler(x.node)
+  def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
-  def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough)).node
-    val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
-    hints.node :=? x
-    hints.node
-  }
 }
 
 /** Synthesizeable unit tests */

src/main/scala/tilelink/Isolation.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.AsyncBundle
@@ -67,17 +66,3 @@ class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implici
     }
   }
 }
-
-object TLIsolation
-{
-  // applied to the TL source node; y.node := TLIsolation(fOut, fIn)(x.node)
-  // f* should insert an isolation gate between the input UInt and its result
-  // fOut is applied to data flowing from client to manager
-  // fIn  is applied to data flowing from manager to client
-  // **** WARNING: the isolation functions must bring the values to 0 ****
-  def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
-    val iso = LazyModule(new TLIsolation(fOut, fIn))
-    iso.node :=? x
-    (iso.node, () => (iso.module.io.iso_out, iso.module.io.iso_in))
-  }
-}

src/main/scala/tilelink/Map.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -39,10 +38,5 @@ class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule
 
 object TLMap
 {
-  // applied to the TL source node; y.node := TLMap(fn)(x.node)
+  def apply(fn: AddressSet => BigInt)(implicit p: Parameters): TLNode = LazyModule(new TLMap(fn)).node
-  def apply(fn: AddressSet => BigInt)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val map = LazyModule(new TLMap(fn))
-    map.node :=? x
-    map.node
-  }
 }

src/main/scala/tilelink/NodeNumberer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 
@@ -56,10 +55,5 @@ class TLNodeNumberer(nodeAddressOffset: Option[Int] = None)(implicit p: Paramete
 
 object TLNodeNumberer
 {
-  // applied to the TL source node; y.node := TLBuffer(x.node)
+  def apply(nodeAddressOffset: Option[Int] = None)(implicit p: Parameters): TLNode = LazyModule(new TLNodeNumberer(nodeAddressOffset)).node
-  def apply(nodeAddressOffset: Option[Int] = None)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val numberer = LazyModule(new TLNodeNumberer(nodeAddressOffset))
-    numberer.node :=? x
-    numberer.node
-  }
 }

src/main/scala/tilelink/RationalCrossing.scala

@@ -10,7 +10,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -79,22 +78,12 @@ class TLRationalCrossingSink(direction: RationalDirection = Symmetric)(implicit
 
 object TLRationalCrossingSource
 {
-  // applied to the TL source node; y.node := TLRationalCrossingSource()(x.node)
+  def apply()(implicit p: Parameters) = LazyModule(new TLRationalCrossingSource).node
-  def apply()(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLRationalOutwardNode = {
-    val source = LazyModule(new TLRationalCrossingSource)
-    source.node :=? x
-    source.node
-  }
 }
 
 object TLRationalCrossingSink
 {
-  // applied to the TL source node; y.node := TLRationalCrossingSink()(x.node)
+  def apply(direction: RationalDirection = Symmetric)(implicit p: Parameters) = LazyModule(new TLRationalCrossingSink(direction)).node
-  def apply(direction: RationalDirection = Symmetric)(x: TLRationalOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val sink = LazyModule(new TLRationalCrossingSink(direction))
-    sink.node :=? x
-    sink.node
-  }
 }
 
 @deprecated("TLRationalCrossing is fragile. Use TLRationalCrossingSource and TLRationalCrossingSink", "rocket-chip 1.2")

src/main/scala/tilelink/SourceShrinker.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -75,10 +74,5 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
 
 object TLSourceShrinker
 {
-  // applied to the TL source node; y.node := TLSourceShrinker(n)(x.node)
+  def apply(maxInFlight: Int)(implicit p: Parameters): TLNode = LazyModule(new TLSourceShrinker(maxInFlight)).node
-  def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
-    shrinker.node :=? x
-    shrinker.node
-  }
 }

src/main/scala/tilelink/ToAHB.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.amba.ahb._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -187,10 +186,5 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
 
 object TLToAHB
 {
-  // applied to the TL source node; y.node := TLToAHB()(x.node)
+  def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAHB(aFlow)).node
-  def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
-    val ahb = LazyModule(new TLToAHB(aFlow))
-    ahb.node :=? x
-    ahb.node
-  }
 }

src/main/scala/tilelink/ToAPB.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.amba.apb._
@@ -86,10 +85,5 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod
 
 object TLToAPB
 {
-  // applied to the TL source node; y.node := TLToAPB()(x.node)
+  def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAPB(aFlow)).node
-  def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): APBOutwardNode = {
-    val apb = LazyModule(new TLToAPB(aFlow))
-    apb.node :=? x
-    apb.node
-  }
 }

src/main/scala/tilelink/ToAXI4.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -215,12 +214,8 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
 
 object TLToAXI4
 {
-  // applied to the TL source node; y.node := TLToAXI4()(x.node)
+  def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(implicit p: Parameters) =
-  def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
+    LazyModule(new TLToAXI4(combinational, adapterName, stripBits)).node
-    val axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits))
-    axi4.node :=? x
-    axi4.node
-  }
 
   def sortByType(a: TLClientParameters, b: TLClientParameters): Boolean = {
     if ( a.supportsProbe && !b.supportsProbe) return false

src/main/scala/tilelink/WidthWidget.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -192,12 +191,7 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
 
 object TLWidthWidget
 {
-  // applied to the TL source node; y.node := WidthWidget(x.node, 16)
+  def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = LazyModule(new TLWidthWidget(innerBeatBytes)).node
-  def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
-    widget.node :=? x
-    widget.node
-  }
 }
 
 /** Synthesizeable unit tests */