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diplomacy: convert all helper objects to return nodes

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This commit is contained in:
Wesley W. Terpstra
2017-10-27 00:45:21 -07:00
parent 41705808dd
commit 6aac658184
26 changed files with 38 additions and 211 deletions
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7
src/main/scala/amba/ahb/ToTL.scala
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@ -3,7 +3,6 @@
package freechips.rocketchip.amba.ahb
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
@ -132,9 +131,5 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
object AHBToTL
{
def apply()(x: AHBOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val tl = LazyModule(new AHBToTL)
tl.node :=? x
tl.node
}
def apply()(implicit p: Parameters) = LazyModule(new AHBToTL).node
}

15
src/main/scala/amba/axi4/AsyncCrossing.scala
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@ -3,7 +3,6 @@
package freechips.rocketchip.amba.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
@ -44,22 +43,12 @@ class AXI4AsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameter
object AXI4AsyncCrossingSource
{
// applied to the AXI4 source node; y.node := AXI4AsyncCrossingSource()(x.node)
def apply(sync: Int = 3)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4AsyncOutwardNode = {
val source = LazyModule(new AXI4AsyncCrossingSource(sync))
source.node :=? x
source.node
}
def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSource(sync)).node
}
object AXI4AsyncCrossingSink
{
// applied to the AXI4 source node; y.node := AXI4AsyncCrossingSink()(x.node)
def apply(depth: Int = 8, sync: Int = 3)(x: AXI4AsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val sink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
sink.node :=? x
sink.node
}
def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSink(depth, sync)).node
}
@deprecated("AXI4AsyncCrossing is fragile. Use AXI4AsyncCrossingSource and AXI4AsyncCrossingSink", "rocket-chip 1.2")

14
src/main/scala/amba/axi4/Buffer.scala
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@ -3,7 +3,6 @@
package freechips.rocketchip.amba.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import chisel3.util.IrrevocableIO
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
@ -46,18 +45,13 @@ class AXI4Buffer(
object AXI4Buffer
{
// applied to the AXI4 source node; y.node := AXI4Buffer(x.node)
def apply() (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(BufferParams.default)(x)
def apply(z: BufferParams) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(z, z)(x)
def apply(aw: BufferParams, br: BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br)(x)
def apply() (implicit p: Parameters): AXI4Node = apply(BufferParams.default)
def apply(z: BufferParams) (implicit p: Parameters): AXI4Node = apply(z, z)
def apply(aw: BufferParams, br: BufferParams)(implicit p: Parameters): AXI4Node = apply(aw, aw, br, aw, br)
def apply(
aw: BufferParams,
w: BufferParams,
b: BufferParams,
ar: BufferParams,
r: BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
buffer.node :=? x
buffer.node
}
r: BufferParams)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Buffer(aw, w, b, ar, r)).node
}

8
src/main/scala/amba/axi4/Deinterleaver.scala
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@ -3,7 +3,6 @@
package freechips.rocketchip.amba.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import chisel3.util.IrrevocableIO
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
@ -100,10 +99,5 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
object AXI4Deinterleaver
{
// applied to the AXI4 source node; y.node := AXI4Deinterleaver()(x.node)
def apply(maxReadBytes: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val deinterleaver = LazyModule(new AXI4Deinterleaver(maxReadBytes))
deinterleaver.node :=? x
deinterleaver.node
}
def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Deinterleaver(maxReadBytes)).node
}

8
src/main/scala/amba/axi4/Fragmenter.scala
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@ -3,7 +3,6 @@
package freechips.rocketchip.amba.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import chisel3.util.IrrevocableIO
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
@ -200,10 +199,5 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
object AXI4Fragmenter
{
// applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node)
def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val fragmenter = LazyModule(new AXI4Fragmenter)
fragmenter.node :=? x
fragmenter.node
}
def apply()(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Fragmenter).node
}

8
src/main/scala/amba/axi4/IdIndexer.scala
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@ -3,7 +3,6 @@
package freechips.rocketchip.amba.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import scala.math.{min,max}
@ -76,10 +75,5 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
object AXI4IdIndexer
{
// applied to the AXI4 source node; y.node := AXI4IdIndexer(idBits)(x.node)
def apply(idBits: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val indexer = LazyModule(new AXI4IdIndexer(idBits))
indexer.node :=? x
indexer.node
}
def apply(idBits: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4IdIndexer(idBits)).node
}

7
src/main/scala/amba/axi4/ToTL.scala
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@ -3,7 +3,6 @@
package freechips.rocketchip.amba.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
@ -161,9 +160,5 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para
object AXI4ToTL
{
def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val tl = LazyModule(new AXI4ToTL)
tl.node :=? x
tl.node
}
def apply()(implicit p: Parameters) = LazyModule(new AXI4ToTL).node
}

8
src/main/scala/amba/axi4/UserYanker.scala
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@ -3,7 +3,6 @@
package freechips.rocketchip.amba.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util.UIntToOH1
@ -92,10 +91,5 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
object AXI4UserYanker
{
// applied to the AXI4 source node; y.node := AXI4UserYanker(idBits, maxFlight)(x.node)
def apply(capMaxFlight: Option[Int] = None)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val yanker = LazyModule(new AXI4UserYanker(capMaxFlight))
yanker.node :=? x
yanker.node
}
def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4UserYanker(capMaxFlight)).node
}