diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 6f7ca640..b58e94a3 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -59,10 +59,6 @@ trait ScalarOpConstants { val RA = UInt(1, 5) } - -trait InterruptConstants { - val CAUSE_INTERRUPT = 32 -} trait VectorOpConstants { val VEC_X = Bits("b??", 2).toUInt diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 97525f0b..22ed8502 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -6,7 +6,7 @@ import uncore.constants.MemoryOpConstants._ import ALU._ import Util._ -class CtrlDpathIO extends Bundle() +class CtrlDpathIO(implicit conf: RocketConfiguration) extends Bundle { // outputs to datapath val sel_pc = UInt(OUTPUT, 3) @@ -42,7 +42,7 @@ class CtrlDpathIO extends Bundle() // exception handling val retire = Bool(OUTPUT) val exception = Bool(OUTPUT) - val cause = UInt(OUTPUT, 6) + val cause = UInt(OUTPUT, conf.xprlen) val badvaddr_wen = Bool(OUTPUT) // high for a load/store access fault // inputs from datapath val inst = Bits(INPUT, 32) @@ -90,12 +90,12 @@ object XDecode extends DecodeConstants // | | | | | | | | | | | | | | | | | | | | | | | fence // | | | | | | | | | | | | | | | | | | | | | | | | amo // | | | | | | | | | | | | | | | | | | | | | | | | | - BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_X, A1_X, IMM_SB,DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), @@ -395,7 +395,7 @@ class Control(implicit conf: RocketConfiguration) extends Module val id_reg_fence = Reg(init=Bool(false)) val sr = io.dpath.status - var id_interrupts = (0 until sr.ip.getWidth).map(i => (sr.im(i) && sr.ip(i), UInt(CAUSE_INTERRUPT+i))) + var id_interrupts = (0 until sr.ip.getWidth).map(i => (sr.im(i) && sr.ip(i), UInt(BigInt(1) << (conf.xprlen-1) | i))) val (id_interrupt_unmasked, id_interrupt_cause) = checkExceptions(id_interrupts) val id_interrupt = io.dpath.status.ei && id_interrupt_unmasked @@ -410,16 +410,18 @@ class Control(implicit conf: RocketConfiguration) extends Module val id_csr_en = id_csr != CSR.N val id_csr_fp = Bool(conf.fpu) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs) val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr) - val id_csr_privileged = id_csr_en && - (id_csr_addr(9,8) != UInt(0) || - id_csr_addr(11,10) != UInt(0) && id_csr_wen) val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr) + val id_csr_privileged = id_csr_en && + (id_csr_addr(11,10) === UInt(3) && id_csr_wen || + id_csr_addr(11,10) === UInt(2) || + id_csr_addr(11,10) === UInt(1) && !io.dpath.status.s || + id_csr_addr(9,8) >= UInt(2) || + id_csr_addr(9,8) === UInt(1) && !io.dpath.status.s && id_csr_wen) // flush pipeline on CSR writes that may have side effects val id_csr_flush = { val safe_csrs = CSRs.sup0 :: CSRs.sup1 :: CSRs.epc :: Nil - id_csr_en && id_csr_wen && DecodeLogic(id_csr_addr, legal_csrs -- safe_csrs, safe_csrs) + id_csr_en && id_csr_wen && !DecodeLogic(id_csr_addr, safe_csrs, legal_csrs -- safe_csrs) } - val id_privileged = id_sret || id_csr_privileged // stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE) val id_amo_aq = io.dpath.inst(26) @@ -433,13 +435,14 @@ class Control(implicit conf: RocketConfiguration) extends Module val (id_xcpt, id_cause) = checkExceptions(List( (id_interrupt, id_interrupt_cause), - (io.imem.resp.bits.xcpt_ma, UInt(0)), - (io.imem.resp.bits.xcpt_if, UInt(1)), - (!id_int_val || id_csr_invalid, UInt(2)), - (id_privileged && !io.dpath.status.s, UInt(3)), - ((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(4)), - (id_syscall, UInt(6)), - (id_rocc_val && !io.dpath.status.er, UInt(12)))) + (io.imem.resp.bits.xcpt_ma, UInt(Causes.misaligned_fetch)), + (io.imem.resp.bits.xcpt_if, UInt(Causes.fault_fetch)), + (!id_int_val || id_csr_invalid, UInt(Causes.illegal_instruction)), + (id_csr_privileged, UInt(Causes.privileged_instruction)), + (id_sret && !io.dpath.status.s, UInt(Causes.privileged_instruction)), + ((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(Causes.fp_disabled)), + (id_syscall, UInt(Causes.syscall)), + (id_rocc_val && !io.dpath.status.er, UInt(Causes.accelerator_disabled)))) ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid when (id_xcpt) { ex_reg_cause := id_cause } @@ -496,7 +499,7 @@ class Control(implicit conf: RocketConfiguration) extends Module val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause), - (ex_reg_fp_val && io.fpu.illegal_rm, UInt(2)))) + (ex_reg_fp_val && io.fpu.illegal_rm, UInt(Causes.illegal_instruction)))) mem_reg_replay := replay_ex && !take_pc_wb mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb && !mem_reg_replay_next @@ -533,10 +536,10 @@ class Control(implicit conf: RocketConfiguration) extends Module val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause), - (mem_reg_mem_val && io.dmem.xcpt.ma.ld, UInt( 8)), - (mem_reg_mem_val && io.dmem.xcpt.ma.st, UInt( 9)), - (mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(10)), - (mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11)))) + (mem_reg_mem_val && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)), + (mem_reg_mem_val && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)), + (mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load)), + (mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(Causes.fault_store)))) val dcache_kill_mem = mem_reg_wen && io.dmem.replay_next.valid // structural hazard on writeback port val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem @@ -645,10 +648,13 @@ class Control(implicit conf: RocketConfiguration) extends Module } // stall for RAW/WAW hazards on PCRs, loads, AMOs, and mul/div in execute stage. + val id_renx1_not0 = id_renx1 && id_raddr1 != UInt(0) + val id_renx2_not0 = id_renx2 && id_raddr2 != UInt(0) + val id_wen_not0 = id_wen && id_waddr != UInt(0) val data_hazard_ex = ex_reg_wen && - (id_renx1.toBool && id_raddr1 === io.dpath.ex_waddr || - id_renx2.toBool && id_raddr2 === io.dpath.ex_waddr || - id_wen.toBool && id_waddr === io.dpath.ex_waddr) + (id_renx1_not0 && id_raddr1 === io.dpath.ex_waddr || + id_renx2_not0 && id_raddr2 === io.dpath.ex_waddr || + id_wen_not0 && id_waddr === io.dpath.ex_waddr) val fp_data_hazard_ex = ex_reg_fp_wen && (io.fpu.dec.ren1 && id_raddr1 === io.dpath.ex_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr || @@ -662,9 +668,9 @@ class Control(implicit conf: RocketConfiguration) extends Module if (conf.fastLoadWord) Bool(!conf.fastLoadByte) && mem_reg_slow_bypass else Bool(true) val data_hazard_mem = mem_reg_wen && - (id_raddr1 != UInt(0) && id_renx1 && id_raddr1 === io.dpath.mem_waddr || - id_raddr2 != UInt(0) && id_renx2 && id_raddr2 === io.dpath.mem_waddr || - id_waddr != UInt(0) && id_wen && id_waddr === io.dpath.mem_waddr) + (id_renx1_not0 && id_raddr1 === io.dpath.mem_waddr || + id_renx2_not0 && id_raddr2 === io.dpath.mem_waddr || + id_wen_not0 && id_waddr === io.dpath.mem_waddr) val fp_data_hazard_mem = mem_reg_fp_wen && (io.fpu.dec.ren1 && id_raddr1 === io.dpath.mem_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr || @@ -683,9 +689,9 @@ class Control(implicit conf: RocketConfiguration) extends Module val id_wb_hazard = fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val) val id_sboard_hazard = - (id_raddr1 != UInt(0) && id_renx1 && sboard.readBypassed(id_raddr1) || - id_raddr2 != UInt(0) && id_renx2 && sboard.readBypassed(id_raddr2) || - id_waddr != UInt(0) && id_wen && sboard.readBypassed(id_waddr)) + (id_renx1_not0 && sboard.readBypassed(id_raddr1) || + id_renx2_not0 && sboard.readBypassed(id_raddr2) || + id_wen_not0 && sboard.readBypassed(id_waddr)) val ctrl_stalld = id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index a767bd6f..8ae151e7 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -281,7 +281,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Module // processor control regfile write pcr.io.rw.addr := wb_reg_inst(31,20) pcr.io.rw.cmd := io.ctrl.csr - pcr.io.rw.wdata := wb_reg_wdata + pcr.io.rw.wdata := Mux(io.ctrl.csr === CSR.S, pcr.io.rw.rdata | wb_reg_wdata, + Mux(io.ctrl.csr === CSR.C, pcr.io.rw.rdata & ~wb_reg_wdata, + wb_reg_wdata)) io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst) io.rocc.cmd.bits.rs1 := wb_reg_wdata diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 1262bc1a..08b463b3 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -98,14 +98,14 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module val ptbr = UInt(OUTPUT, PADDR_BITS) val evec = UInt(OUTPUT, VADDR_BITS+1) val exception = Bool(INPUT) - val retire = Bool(INPUT) - val cause = UInt(INPUT, 6) + val retire = UInt(INPUT, log2Up(1+conf.retireWidth)) + val cause = UInt(INPUT, conf.xprlen) val badvaddr_wen = Bool(INPUT) val pc = UInt(INPUT, VADDR_BITS+1) val sret = Bool(INPUT) val fatc = Bool(OUTPUT) val replay = Bool(OUTPUT) - val time = UInt(OUTPUT, 64) + val time = UInt(OUTPUT, conf.xprlen) val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ) val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip } @@ -114,7 +114,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module val reg_badvaddr = Reg(Bits(width = VADDR_BITS)) val reg_evec = Reg(Bits(width = VADDR_BITS)) val reg_compare = Reg(Bits(width = 32)) - val reg_cause = Reg(Bits(width = io.cause.getWidth)) + val reg_cause = Reg(Bits(width = conf.xprlen)) val reg_tohost = Reg(init=Bits(0, conf.xprlen)) val reg_fromhost = Reg(init=Bits(0, conf.xprlen)) val reg_sup0 = Reg(Bits(width = conf.xprlen)) @@ -122,8 +122,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module val reg_ptbr = Reg(UInt(width = PADDR_BITS)) val reg_stats = Reg(init=Bool(false)) val reg_status = Reg(new Status) // reset down below - val reg_time = WideCounter(64) - val reg_instret = WideCounter(64, io.retire) + val reg_time = WideCounter(conf.xprlen) + val reg_instret = WideCounter(conf.xprlen, io.retire) val reg_fflags = Reg(UInt(width = 5)) val reg_frm = Reg(UInt(width = 3)) @@ -208,7 +208,6 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module val read_impl = Bits(2) val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS - val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0) val read_mapping = Map[Int,Bits]( CSRs.fflags -> (if (conf.fpu) reg_fflags else UInt(0)), @@ -226,7 +225,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module CSRs.count -> reg_time, CSRs.compare -> reg_compare, CSRs.evec -> reg_evec, - CSRs.cause -> read_cause, + CSRs.cause -> reg_cause, CSRs.status -> io.status.toBits, CSRs.hartid -> io.host.id, CSRs.impl -> read_impl, @@ -246,11 +245,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module when (wen) { when (decoded_addr(CSRs.status)) { - val sr_wdata = Mux(io.rw.cmd === CSR.S, reg_status.toBits | wdata, - Mux(io.rw.cmd === CSR.C, reg_status.toBits & ~wdata, - wdata)) - reg_status := new Status().fromBits(sr_wdata) - + reg_status := new Status().fromBits(wdata) reg_status.s64 := true reg_status.u64 := true reg_status.zero := 0 @@ -258,22 +253,20 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module if (conf.rocc.isEmpty) reg_status.er := false if (!conf.fpu) reg_status.ef := false } - when (io.rw.cmd != CSR.C && io.rw.cmd != CSR.S) { - when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata } - when (decoded_addr(CSRs.frm)) { reg_frm := wdata } - when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth } - when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt } - when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt } - when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt } - when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) } - when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } } - when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } } - when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) } - when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata } - when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata } - when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt } - when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) } - } + when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata } + when (decoded_addr(CSRs.frm)) { reg_frm := wdata } + when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth } + when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt } + when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt } + when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt } + when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) } + when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } } + when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } } + when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) } + when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata } + when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata } + when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt } + when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) } } io.host.ipi_rep.ready := Bool(true) diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index b41b4265..15c3f83f 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -212,6 +212,7 @@ class FPToInt extends Module val unrec_s = hardfloat.recodedFloatNToFloatN(in.in1, 23, 9) val unrec_d = hardfloat.recodedFloatNToFloatN(in.in1, 52, 12) + val unrec_out = Mux(in.single, Cat(Fill(32, unrec_s(31)), unrec_s), unrec_d) val dcmp = Module(new hardfloat.recodedFloatNCompare(52, 12)) dcmp.io.a := in.in1 @@ -221,7 +222,8 @@ class FPToInt extends Module val d2i = hardfloat.recodedFloatNToAny(in.in1, in.rm, ~in.cmd(1,0), 52, 12, 64) - io.out.bits.toint := Mux(in.single, Cat(Fill(32, unrec_s(31)), unrec_s), unrec_d) + io.out.bits.toint := unrec_out + io.out.bits.store := unrec_out io.out.bits.exc := Bits(0) when (in.cmd === FCMD_CVT_W_FMT || in.cmd === FCMD_CVT_WU_FMT) { @@ -238,7 +240,6 @@ class FPToInt extends Module } io.out.valid := valid - io.out.bits.store := Mux(in.single, Cat(unrec_d(63,32), unrec_s), unrec_d) io.out.bits.lt := dcmp.io.a_lt_b } @@ -268,7 +269,7 @@ class IntToFP(val latency: Int) extends Module mux.exc := Bits(0) mux.data := hardfloat.floatNToRecodedFloatN(in.bits.data, 52, 12) when (in.bits.single) { - mux.data := hardfloat.floatNToRecodedFloatN(in.bits.data, 23, 9) + mux.data := Cat(SInt(-1, 32), hardfloat.floatNToRecodedFloatN(in.bits.data, 23, 9)) } when (in.bits.cmd === FCMD_CVT_FMT_W || in.bits.cmd === FCMD_CVT_FMT_WU || @@ -463,7 +464,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val load_wb_tag = RegEnable(io.dpath.dmem_resp_tag, io.dpath.dmem_resp_val) val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9) val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12) - val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1), rec_s), rec_d) + val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1, 32), rec_s), rec_d) // regfile val regfile = Mem(Bits(width = 65), 32) @@ -525,7 +526,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits.data, fpmu.io.out.bits.exc), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits.data, ifpu.io.out.bits.exc), - Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, sfma.io.out, sfma.io.exc), + Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, Cat(SInt(-1, 32), sfma.io.out), sfma.io.exc), Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out, dfma.io.exc)) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 8a60548b..88742586 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -5,11 +5,11 @@ import uncore._ import Util._ case class ICacheConfig(sets: Int, assoc: Int, + ibytes: Int = 4, ntlb: Int = 8, nbtb: Int = 8, code: Code = new IdentityCode) { val w = 1 - val ibytes = 4 val dm = assoc == 1 val lines = sets * assoc @@ -248,7 +248,7 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout) val finish_q = Module(new Queue(new GrantAck, 1)) - finish_q.io.enq.valid := refill_done && tl.co.requiresAck(io.mem.grant.bits.payload) + finish_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(io.mem.grant.bits.payload.g_type) finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id // output signals diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index 5acb84a8..2d91d92c 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -5,14 +5,14 @@ import Node._ /* Automatically generated by parse-opcodes */ object Instructions { - def JAL = Bits("b?????????????????????????1101111") - def JALR = Bits("b?????????????????000?????1100111") def BEQ = Bits("b?????????????????000?????1100011") def BNE = Bits("b?????????????????001?????1100011") def BLT = Bits("b?????????????????100?????1100011") def BGE = Bits("b?????????????????101?????1100011") def BLTU = Bits("b?????????????????110?????1100011") def BGEU = Bits("b?????????????????111?????1100011") + def JALR = Bits("b?????????????????000?????1100111") + def JAL = Bits("b?????????????????????????1101111") def LUI = Bits("b?????????????????????????0110111") def AUIPC = Bits("b?????????????????????????0010111") def ADDI = Bits("b?????????????????000?????0010011") @@ -185,6 +185,36 @@ object Instructions { def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011") def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011") } +object Causes { + val misaligned_fetch = 0x0 + val fault_fetch = 0x1 + val illegal_instruction = 0x2 + val privileged_instruction = 0x3 + val fp_disabled = 0x4 + val syscall = 0x6 + val breakpoint = 0x7 + val misaligned_load = 0x8 + val misaligned_store = 0x9 + val fault_load = 0xa + val fault_store = 0xb + val accelerator_disabled = 0xc + val all = { + val res = collection.mutable.ArrayBuffer[Int]() + res += misaligned_fetch + res += fault_fetch + res += illegal_instruction + res += privileged_instruction + res += fp_disabled + res += syscall + res += breakpoint + res += misaligned_load + res += misaligned_store + res += fault_load + res += fault_store + res += accelerator_disabled + res.toArray + } +} object CSRs { val fflags = 0x1 val frm = 0x2 diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index ba08110c..7eb5b15d 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -260,7 +260,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte } val ackq = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1)) - ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAck(io.mem_grant.bits.payload) + ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type) ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp @@ -686,12 +686,12 @@ class AMOALU(implicit conf: DCacheConfig) extends Module { class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle { val kill = Bool() - val typ = Bits(width = 3) + val typ = Bits(width = MT_SZ) val phys = Bool() val addr = UInt(width = conf.maxaddrbits) val data = Bits(width = conf.databits) val tag = Bits(width = conf.reqtagbits) - val cmd = Bits(width = 4) + val cmd = Bits(width = M_SZ) } class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle { diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala index ca2926fc..0fcb6580 100644 --- a/rocket/src/main/scala/package.scala +++ b/rocket/src/main/scala/package.scala @@ -1,6 +1,5 @@ package object rocket extends rocket.constants.ScalarOpConstants with - rocket.constants.InterruptConstants with rocket.constants.VectorOpConstants { val START_ADDR = 0x2000 diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 618a30bc..1791e6f8 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -7,6 +7,7 @@ import Util._ case class RocketConfiguration(tl: TileLinkConfiguration, icache: ICacheConfig, dcache: DCacheConfig, fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None, + retireWidth: Int = 1, vm: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, @@ -19,7 +20,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration, if (fastLoadByte) require(fastLoadWord) } -class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent +class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) { val memPorts = 2 + !confIn.rocc.isEmpty // Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc val dcachePortId = 0 @@ -31,6 +32,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module implicit val icConf = confIn.icache implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(dcachePorts), databits = confIn.xprlen) implicit val conf = confIn.copy(dcache = dcConf) + require(conf.retireWidth == 1) // for now... val io = new Bundle { val tilelink = new TileLinkIO diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 09dc7e8b..7735847c 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -109,17 +109,21 @@ object Split } // a counter that clock gates most of its MSBs using the LSB carry-out -case class WideCounter(width: Int, inc: Bool = Bool(true)) +case class WideCounter(width: Int, inc: UInt = UInt(1)) { - private val isWide = width >= 4 - private val smallWidth = if (isWide) log2Up(width) else width + require(inc.getWidth > 0) + private val isWide = width > 2*inc.getWidth + private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val small = Reg(init=UInt(0, smallWidth)) - private val nextSmall = small + UInt(1, smallWidth+1) - when (inc) { small := nextSmall(smallWidth-1,0) } + private val doInc = inc.orR + private val nextSmall = + if (inc.getWidth == 1) small + UInt(1, smallWidth+1) + else Cat(UInt(0,1), small) + inc + when (doInc) { small := nextSmall(smallWidth-1,0) } private val large = if (isWide) { val r = Reg(init=UInt(0, width - smallWidth)) - when (inc && nextSmall(smallWidth)) { r := r + UInt(1) } + when (doInc && nextSmall(smallWidth)) { r := r + UInt(1) } r } else null