factor out unit tests into separate package
This commit is contained in:
Howard Mao
138
groundtest/src/main/scala/common/Tile.scala
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138
groundtest/src/main/scala/common/Tile.scala
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package groundtest.common
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import Chisel._
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import rocket._
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import uncore.tilelink._
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import junctions._
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import scala.util.Random
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import scala.collection.mutable.ListBuffer
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import cde.{Parameters, Field}
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case object BuildGroundTest extends Field[Parameters => GroundTest]
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case class GroundTestTileSettings(
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uncached: Int = 0, cached: Int = 0, ptw: Int = 0,
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maxXacts: Int = 1, csrs: Int = 0)
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case object GroundTestKey extends Field[Seq[GroundTestTileSettings]]
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case object GroundTestId extends Field[Int]
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trait HasGroundTestConstants {
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val timeoutCodeBits = 4
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val errorCodeBits = 4
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}
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trait HasGroundTestParameters extends HasAddrMapParameters {
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implicit val p: Parameters
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val tileId = p(GroundTestId)
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val tileSettings = p(GroundTestKey)(tileId)
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val nUncached = tileSettings.uncached
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val nCached = tileSettings.cached
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val nPTW = tileSettings.ptw
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val memStart = addrMap("mem").start
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val memStartBlock = memStart >> p(CacheBlockOffsetBits)
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}
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class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestors = Vec(n, new TLBPTWIO).flip
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}
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val req_arb = Module(new RRArbiter(new PTWReq, n))
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req_arb.io.in <> io.requestors.map(_.req)
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req_arb.io.out.ready := Bool(true)
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def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
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class QueueChannel extends ParameterizedBundle()(p) {
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val ppn = UInt(width = ppnBits)
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val chosen = UInt(width = log2Up(n))
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}
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val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
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val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
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val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
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val s2_valid = Reg(next = req_arb.io.out.valid)
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val s2_resp = Wire(new PTWResp)
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s2_resp.pte.ppn := s2_ppn
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s2_resp.pte.reserved_for_software := UInt(0)
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s2_resp.pte.d := Bool(true)
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s2_resp.pte.a := Bool(false)
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s2_resp.pte.g := Bool(false)
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s2_resp.pte.u := Bool(true)
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s2_resp.pte.r := Bool(true)
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s2_resp.pte.w := Bool(true)
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s2_resp.pte.x := Bool(false)
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s2_resp.pte.v := Bool(true)
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io.requestors.zipWithIndex.foreach { case (requestor, i) =>
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requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
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requestor.resp.bits := s2_resp
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requestor.status.vm := UInt("b01000")
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requestor.status.prv := UInt(PRV.S)
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requestor.invalidate := Bool(false)
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}
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}
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class GroundTestStatus extends Bundle with HasGroundTestConstants {
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val finished = Bool(OUTPUT)
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val timeout = Valid(UInt(width = timeoutCodeBits))
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val error = Valid(UInt(width = errorCodeBits))
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}
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class GroundTestIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasGroundTestParameters {
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val cache = Vec(nCached, new HellaCacheIO)
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val mem = Vec(nUncached, new ClientUncachedTileLinkIO)
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val ptw = Vec(nPTW, new TLBPTWIO)
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val status = new GroundTestStatus
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}
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abstract class GroundTest(implicit val p: Parameters) extends Module
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with HasGroundTestParameters {
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val io = new GroundTestIO
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}
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class GroundTestTile(resetSignal: Bool)
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(implicit val p: Parameters)
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extends Tile(resetSignal = resetSignal)(p)
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with HasGroundTestParameters {
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val test = p(BuildGroundTest)(dcacheParams)
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val ptwPorts = ListBuffer.empty ++= test.io.ptw
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val memPorts = ListBuffer.empty ++= test.io.mem
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if (nCached > 0) {
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val dcache_io =
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if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io
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else Module(new HellaCache()(dcacheParams)).io
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val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
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dcacheArb.io.requestor.zip(test.io.cache).foreach {
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case (requestor, cache) =>
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val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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dcacheIF.io.requestor <> cache
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requestor <> dcacheIF.io.cache
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}
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dcache_io.cpu <> dcacheArb.io.mem
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io.cached.head <> dcache_io.mem
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// SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false
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dcache_io.cpu.invalidate_lr := Bool(false)
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ptwPorts += dcache_io.ptw
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}
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when (test.io.status.finished) { stop() }
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if (ptwPorts.size > 0) {
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val ptw = Module(new DummyPTW(ptwPorts.size))
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ptw.io.requestors <> ptwPorts
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}
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require(memPorts.size == io.uncached.size)
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if (memPorts.size > 0) {
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io.uncached <> memPorts
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}
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}
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222
groundtest/src/main/scala/common/Util.scala
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222
groundtest/src/main/scala/common/Util.scala
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package groundtest.common
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import Chisel._
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// ============
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// Static timer
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// ============
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// Timer with a statically-specified period.
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// Can take multiple inflight start-stop events with ID
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// Will continue to count down so long as at least one inflight event
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class Timer(initCount: Int, maxInflight: Int) extends Module {
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val io = new Bundle {
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val start = Valid(UInt(width = log2Up(maxInflight))).flip
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val stop = Valid(UInt(width = log2Up(maxInflight))).flip
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val timeout = Bool(OUTPUT)
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}
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val inflight = Reg(init = Vec.fill(maxInflight) { Bool(false) })
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val countdown = Reg(UInt(width = log2Up(initCount)))
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val active = inflight.reduce(_ || _)
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when (active) {
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countdown := countdown - UInt(1)
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}
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when (io.start.valid) {
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inflight(io.start.bits) := Bool(true)
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countdown := UInt(initCount - 1)
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}
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when (io.stop.valid) {
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inflight(io.stop.bits) := Bool(false)
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}
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io.timeout := countdown === UInt(0) && active
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}
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object Timer {
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def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
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val timer = Module(new Timer(initCount, 1))
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timer.io.start.valid := start
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timer.io.start.bits := UInt(0)
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timer.io.stop.valid := stop
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timer.io.stop.bits := UInt(0)
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timer.io.timeout
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}
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}
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// =============
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// Dynamic timer
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// =============
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// Timer with a dynamically-settable period.
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class DynamicTimer(w: Int) extends Module {
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val io = new Bundle {
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val start = Bool(INPUT)
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val period = UInt(INPUT, w)
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val stop = Bool(INPUT)
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val timeout = Bool(OUTPUT)
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}
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val countdown = Reg(init = UInt(0, w))
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val active = Reg(init = Bool(false))
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when (io.start) {
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countdown := io.period
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active := Bool(true)
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}
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.elsewhen (io.stop) {
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active := Bool(false)
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}
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.elsewhen (active) {
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countdown := countdown - UInt(1)
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}
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io.timeout := countdown === UInt(0) && active
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}
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// ============
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// LCG16 module
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// ============
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// A 16-bit psuedo-random generator based on a linear conguential
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// generator (LCG). The state is stored in an unitialised register.
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// When using the C++ backend, it is straigtforward to arrange a
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// random initial value for each uninitialised register, effectively
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// seeding each LCG16 instance with a different seed.
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class LCG16 extends Module {
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val io = new Bundle {
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val out = UInt(OUTPUT, 16)
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}
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val state = Reg(UInt(width = 32))
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state := state * UInt(1103515245, 32) + UInt(12345, 32)
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io.out := state(30, 15)
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}
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// ==========
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// LCG module
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// ==========
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// An n-bit psuedo-random generator made from many instances of a
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// 16-bit LCG. Parameter 'width' must be larger than 0.
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class LCG(val w : Int) extends Module {
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val io = new Bundle {
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val out = UInt(OUTPUT, w)
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}
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require(w > 0)
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val numLCG16s : Int = (w+15)/16
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val outs = List.fill(numLCG16s)(Module(new LCG16()).io.out)
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io.out := Cat( outs(0)((w%16)-1, 0)
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, outs.drop(1) : _*)
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}
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// ======================
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// Frequency distribution
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// ======================
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// Given a list of (frequency, value) pairs, return a random value
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// according to the frequency distribution. The sum of the
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// frequencies in the distribution must be a power of two.
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object Frequency {
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def apply(dist : List[(Int, Bits)]) : Bits = {
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// Distribution must be non-empty
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require(dist.length > 0)
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// Require that the frequencies sum to a power of two
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val (freqs, vals) = dist.unzip
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val total = freqs.sum
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require(isPow2(total))
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// First item in the distribution
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val (firstFreq, firstVal) = dist.head
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// Result wire
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val result = Wire(Bits(width = firstVal.getWidth))
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result := UInt(0)
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// Random value
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val randVal = Module(new LCG(log2Up(total))).io.out
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// Pick return value
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var count = firstFreq
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var select = when (randVal < UInt(firstFreq)) { result := firstVal }
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for (p <- dist.drop(1)) {
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count = count + p._1
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select = select.elsewhen(randVal < UInt(count)) { result := p._2 }
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}
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return result
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}
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}
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object ValidMux {
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def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
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apply(v1 +: v2.toSeq)
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}
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def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
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val out = Wire(Valid(valids.head.bits))
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out.valid := valids.map(_.valid).reduce(_ || _)
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out.bits := MuxCase(valids.head.bits,
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valids.map(v => (v.valid -> v.bits)))
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out
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}
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}
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object DebugCombiner {
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def apply(debugs: Seq[GroundTestStatus]): GroundTestStatus = {
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val out = Wire(new GroundTestStatus)
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out.finished := debugs.map(_.finished).reduce(_ || _)
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out.timeout := ValidMux(debugs.map(_.timeout))
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out.error := ValidMux(debugs.map(_.error))
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out
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}
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}
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/**
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* Takes in data on one decoupled interface and broadcasts it to
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* N decoupled output interfaces
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*/
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class Broadcaster[T <: Data](typ: T, n: Int) extends Module {
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val io = new Bundle {
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val in = Decoupled(typ).flip
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val out = Vec(n, Decoupled(typ))
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}
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require (n > 0)
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if (n == 1) {
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io.out.head <> io.in
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} else {
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val idx = Reg(init = UInt(0, log2Up(n)))
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val save = Reg(typ)
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io.out.head.valid := idx === UInt(0) && io.in.valid
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io.out.head.bits := io.in.bits
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for (i <- 1 until n) {
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io.out(i).valid := idx === UInt(i)
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io.out(i).bits := save
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}
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io.in.ready := io.out.head.ready && idx === UInt(0)
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when (io.in.fire()) { save := io.in.bits }
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when (io.out(idx).fire()) {
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when (idx === UInt(n - 1)) { idx := UInt(0) }
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.otherwise { idx := idx + UInt(1) }
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}
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}
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}
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object Broadcaster {
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def apply[T <: Data](in: DecoupledIO[T], n: Int): Vec[DecoupledIO[T]] = {
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val split = Module(new Broadcaster(in.bits, n))
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split.io.in <> in
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split.io.out
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}
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}
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