[tilelink2] Add unit tests for many TL2 components

These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.

src/main/scala/uncore/tilelink2/Fuzzer.scala

@@ -2,8 +2,6 @@
 package uncore.tilelink2
 
 import Chisel._
-import unittest._
-import util.Pow2ClockDivider
 
 class IDMapGenerator(numIds: Int) extends Module {
   val w = log2Up(numIds)
@@ -208,6 +206,9 @@ class TLFuzzer(
   }
 }
 
+/** Synthesizeable integration test */
+import unittest._
+
 class TLFuzzRAM extends LazyModule
 {
   val model = LazyModule(new TLRAMModel)
@@ -231,7 +232,7 @@ class TLFuzzRAM extends LazyModule
     io.finished := fuzz.module.io.finished
 
     // Shove the RAM into another clock domain
-    val clocks = Module(new Pow2ClockDivider(2))
+    val clocks = Module(new util.Pow2ClockDivider(2))
     ram.module.clock := clocks.io.clock_out
 
     // ... and safely cross TL2 into it