Merge pull request #1247 from freechipsproject/misa-c
Implement misa.C proposal
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commit
69b48b623a
@ -837,6 +837,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) }
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when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) }
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}
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}
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}
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}
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def formEPC(x: UInt) = ~(~x | Cat(!reg_misa('c'-'a'), UInt(1)))
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def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U))
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def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
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def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
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}
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}
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@ -228,12 +228,14 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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bpu.io.pc := ibuf.io.pc
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bpu.io.pc := ibuf.io.pc
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bpu.io.ea := mem_reg_wdata
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bpu.io.ea := mem_reg_wdata
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val id_pc_misaligned = !csr.io.status.isa('c'-'a') && ibuf.io.pc(1)
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val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0
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val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0
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val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1
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val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1
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val (id_xcpt, id_cause) = checkExceptions(List(
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val (id_xcpt, id_cause) = checkExceptions(List(
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(csr.io.interrupt, csr.io.interrupt_cause),
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(csr.io.interrupt, csr.io.interrupt_cause),
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(bpu.io.debug_if, UInt(CSR.debugTriggerCause)),
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(bpu.io.debug_if, UInt(CSR.debugTriggerCause)),
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(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
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(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
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(id_pc_misaligned, UInt(Causes.misaligned_fetch)),
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(id_xcpt0.pf.inst, UInt(Causes.fetch_page_fault)),
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(id_xcpt0.pf.inst, UInt(Causes.fetch_page_fault)),
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(id_xcpt0.ae.inst, UInt(Causes.fetch_access)),
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(id_xcpt0.ae.inst, UInt(Causes.fetch_access)),
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(id_xcpt1.pf.inst, UInt(Causes.fetch_page_fault)),
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(id_xcpt1.pf.inst, UInt(Causes.fetch_page_fault)),
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@ -427,14 +429,14 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
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val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
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val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)
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val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)
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val (mem_new_xcpt, mem_new_cause) = checkExceptions(List(
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val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List(
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(mem_debug_breakpoint, UInt(CSR.debugTriggerCause)),
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(mem_debug_breakpoint, UInt(CSR.debugTriggerCause)),
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(mem_breakpoint, UInt(Causes.breakpoint)),
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(mem_breakpoint, UInt(Causes.breakpoint))))
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(mem_npc_misaligned, UInt(Causes.misaligned_fetch))))
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val (mem_xcpt, mem_cause) = checkExceptions(List(
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val (mem_xcpt, mem_cause) = checkExceptions(List(
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(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
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(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
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(mem_reg_valid && mem_new_xcpt, mem_new_cause)))
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(mem_reg_valid && mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
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(mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause)))
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val memCoverCauses = (exCoverCauses ++ List(
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val memCoverCauses = (exCoverCauses ++ List(
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(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
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(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
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@ -677,7 +679,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
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io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
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io.dmem.invalidate_lr := wb_xcpt
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io.dmem.invalidate_lr := wb_xcpt
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io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill((xLen max fLen) / fLen, io.fpu.store_data), mem_reg_rs2))
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io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill((xLen max fLen) / fLen, io.fpu.store_data), mem_reg_rs2))
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io.dmem.s1_kill := killm_common || mem_breakpoint
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io.dmem.s1_kill := killm_common || mem_ldst_xcpt
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io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
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io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
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io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
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io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
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