riscv/rocket-chip
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refactor NASTI to not use param

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This commit is contained in:
Henry Cook 2015-10-02 14:20:47 -07:00
parent 19656e4abe
commit 69a4dd0a79
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/tlb.scala
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@ -10,6 +10,7 @@ import scala.math._
case object NTLBEntries extends Field[Int] case object NTLBEntries extends Field[Int]
abstract trait TLBParameters extends CoreParameters { abstract trait TLBParameters extends CoreParameters {
val addrMap = new AddrHashMap(params(NastiAddrMap))
val entries = params(NTLBEntries) val entries = params(NTLBEntries)
val camAddrBits = ceil(log(entries)/log(2)).toInt val camAddrBits = ceil(log(entries)/log(2)).toInt
val camTagBits = asIdBits + vpnBits val camTagBits = asIdBits + vpnBits
@ -167,7 +168,6 @@ class TLB extends TLBModule {
plru.access(OHToUInt(tag_cam.io.hits)) plru.access(OHToUInt(tag_cam.io.hits))
} }
val addrMap = params(NASTIAddrHashMap)
val paddr = Cat(io.resp.ppn, UInt(0, pgIdxBits)) val paddr = Cat(io.resp.ppn, UInt(0, pgIdxBits))
val addr_ok = addrMap.isValid(paddr) val addr_ok = addrMap.isValid(paddr)
val addr_prot = addrMap.getProt(paddr) val addr_prot = addrMap.getProt(paddr)