From 696dd102eba0d649b857d622701818d06c719711 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sun, 27 Jan 2013 10:59:41 -0800 Subject: [PATCH] cleans up unconnected tile io pins (networking headers overwritten at top level) --- rocket/src/main/scala/tile.scala | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index b4ddbd05..09bc1a03 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -50,6 +50,14 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon io.tilelink.release <> dcache.io.mem.release io.tilelink.release_data <> dcache.io.mem.release_data + val ioSubBundles = arbiter.io.getClass.getMethods.filter( x => + classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => + m.invoke(arbiter.io).asInstanceOf[DirectionalFIFOIO[LogicalNetworkIO[Data]]] } + ioSubBundles.foreach{ m => + m.bits.header.dst := UFix(0) + m.bits.header.src := UFix(0) + } + if (conf.vec) { val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB) arbiter.io.requestor(2) <> vicache.io.mem