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hasti: work-around unsupported 0-width signals

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Wesley W. Terpstra 2016-06-01 10:47:02 -07:00 committed by Andrew Waterman
parent 8983b0e865
commit 695be2f0ae
1 changed files with 8 additions and 5 deletions
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13
junctions/src/main/scala/hasti.scala
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@ -54,7 +54,7 @@ trait HasHastiParameters {
val hastiAddrBits = hastiParams.addrBits val hastiAddrBits = hastiParams.addrBits
val hastiDataBits = hastiParams.dataBits val hastiDataBits = hastiParams.dataBits
val hastiDataBytes = hastiDataBits/8 val hastiDataBytes = hastiDataBits/8
val hastiAlignment = log2Up(hastiDataBytes) val hastiAlignment = log2Ceil(hastiDataBytes)
} }
abstract class HastiModule(implicit val p: Parameters) extends Module abstract class HastiModule(implicit val p: Parameters) extends Module
@ -461,12 +461,15 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
// Calculate the bitmask of which bytes are being accessed // Calculate the bitmask of which bytes are being accessed
val mask_decode = Vec.tabulate(hastiAlignment+1) (UInt(_) <= io.hsize) val mask_decode = Vec.tabulate(hastiAlignment+1) (UInt(_) <= io.hsize)
val mask_wide = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Up(i+1)) } val mask_wide = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Up(i+1)) }
val mask_shift = mask_wide.toBits().asUInt() << io.haddr(hastiAlignment-1,0) val mask_shift = if (hastiAlignment == 0) UInt(1) else
mask_wide.toBits().asUInt() << io.haddr(hastiAlignment-1,0)
// The request had better have been aligned! (AHB-lite requires this) // The request had better have been aligned! (AHB-lite requires this)
assert (io.htrans === HTRANS_IDLE || io.htrans === HTRANS_BUSY || if (hastiAlignment >= 1) {
(io.haddr & mask_decode.toBits()(hastiAlignment,1).asUInt) === UInt(0), assert (io.htrans === HTRANS_IDLE || io.htrans === HTRANS_BUSY ||
"HASTI request not aligned") (io.haddr & mask_decode.toBits()(hastiAlignment,1).asUInt) === UInt(0),
"HASTI request not aligned")
}
// The mask and address during the address phase // The mask and address during the address phase
val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ) val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)