riscv/rocket-chip
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Rationalize ALU function encoding

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MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
This commit is contained in:
Andrew Waterman 2018-02-05 17:50:01 -08:00
parent c1eb795aba
commit 69441930b5
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/ALU.scala
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@ -33,8 +33,8 @@ object ALU
def FN_MUL = FN_ADD def FN_MUL = FN_ADD
def FN_MULH = FN_SL def FN_MULH = FN_SL
def FN_MULHSU = FN_SLT def FN_MULHSU = FN_SEQ
def FN_MULHU = FN_SLTU def FN_MULHU = FN_SNE
def isMulFN(fn: UInt, cmp: UInt) = fn(1,0) === cmp(1,0) def isMulFN(fn: UInt, cmp: UInt) = fn(1,0) === cmp(1,0)
def isSub(cmd: UInt) = cmd(3) def isSub(cmd: UInt) = cmd(3)