refactor arbiter priorities
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f641b44fb8
commit
6847160343
@ -234,7 +234,11 @@ object Constants
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val VIMM_ALU = UFix(1, 1)
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val VIMM_X = UFix(0, 1)
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val DTLB_VEC = 0
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val DTLB_VPF = 1
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val DTLB_CPU = 2
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val DTLB_CPU = 0
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val DTLB_VEC = 1
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val DTLB_VPF = 2
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val DMEM_CPU = 0
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val DMEM_PTW = 1
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val DMEM_VU = 2
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}
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@ -93,15 +93,15 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
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dtlb.io.invalidate := dpath.io.ptbr_wen
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dtlb.io.status := dpath.io.ctrl.status
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arb.io.requestor(0).req_ppn := dtlb.io.cpu_resp.ppn;
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ctrl.io.dmem.req_rdy := dtlb.io.cpu_req.ready && arb.io.requestor(0).req_rdy;
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arb.io.requestor(DMEM_CPU).req_ppn := dtlb.io.cpu_resp.ppn
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ctrl.io.dmem.req_rdy := dtlb.io.cpu_req.ready && arb.io.requestor(DMEM_CPU).req_rdy
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// connect page table walker to TLBs, page table base register (from PCR)
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// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
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ptw.io.dtlb <> dtlb.io.ptw;
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ptw.io.itlb <> itlb.io.ptw;
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ptw.io.ptbr := dpath.io.ptbr;
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arb.io.requestor(1) <> ptw.io.dmem
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arb.io.requestor(DMEM_PTW) <> ptw.io.dmem
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arb.io.dmem <> io.dmem
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ctrl.io.dpath <> dpath.io.ctrl;
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@ -126,8 +126,8 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
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io.imem.itlb_miss := itlb.io.cpu.resp_miss;
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// connect arbiter to ctrl+dpath+DTLB
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arb.io.requestor(0) <> ctrl.io.dmem
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arb.io.requestor(0) <> dpath.io.dmem
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arb.io.requestor(DMEM_CPU) <> ctrl.io.dmem
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arb.io.requestor(DMEM_CPU) <> dpath.io.dmem
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var fpu: rocketFPU = null
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if (HAVE_FPU)
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@ -198,22 +198,22 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
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storegen.io.typ := vu.io.dmem_req.bits.typ
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storegen.io.din := vu.io.dmem_req.bits.data
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arb.io.requestor(2).req_val := vu.io.dmem_req.valid
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arb.io.requestor(2).req_kill := Reg(vu.io.dmem_req.bits.kill)
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arb.io.requestor(2).req_cmd := vu.io.dmem_req.bits.cmd
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arb.io.requestor(2).req_type := vu.io.dmem_req.bits.typ
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arb.io.requestor(2).req_idx := vu.io.dmem_req.bits.idx
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arb.io.requestor(2).req_ppn := Reg(vu.io.dmem_req.bits.ppn)
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arb.io.requestor(2).req_data := Reg(storegen.io.dout)
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arb.io.requestor(2).req_tag := vu.io.dmem_req.bits.tag
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arb.io.requestor(DMEM_VU).req_val := vu.io.dmem_req.valid
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arb.io.requestor(DMEM_VU).req_kill := Reg(vu.io.dmem_req.bits.kill)
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arb.io.requestor(DMEM_VU).req_cmd := vu.io.dmem_req.bits.cmd
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arb.io.requestor(DMEM_VU).req_type := vu.io.dmem_req.bits.typ
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arb.io.requestor(DMEM_VU).req_idx := vu.io.dmem_req.bits.idx
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arb.io.requestor(DMEM_VU).req_ppn := Reg(vu.io.dmem_req.bits.ppn)
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arb.io.requestor(DMEM_VU).req_data := Reg(storegen.io.dout)
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arb.io.requestor(DMEM_VU).req_tag := vu.io.dmem_req.bits.tag
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vu.io.dmem_resp.valid := Reg(arb.io.requestor(2).resp_val)
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vu.io.dmem_resp.valid := Reg(arb.io.requestor(DMEM_VU).resp_val)
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// the vu doesn't look at the ready signal, it's simply a nack
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// but should be delayed one cycle to match the nack semantics
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vu.io.dmem_resp.bits.nack := arb.io.requestor(2).resp_nack || Reg(!arb.io.requestor(2).req_rdy)
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vu.io.dmem_resp.bits.data := arb.io.requestor(2).resp_data_subword
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vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(2).resp_tag)
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vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(2).resp_type)
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vu.io.dmem_resp.bits.nack := arb.io.requestor(DMEM_VU).resp_nack || Reg(!arb.io.requestor(DMEM_VU).req_rdy)
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vu.io.dmem_resp.bits.data := arb.io.requestor(DMEM_VU).resp_data_subword
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vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DMEM_VU).resp_tag)
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vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DMEM_VU).resp_type)
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// share vector integer multiplier with rocket
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dpath.io.vec_imul_req <> vu.io.cp_imul_req
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@ -225,7 +225,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
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}
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else
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{
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arb.io.requestor(2).req_val := Bool(false)
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arb.io.requestor(DMEM_VU).req_val := Bool(false)
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if (HAVE_FPU)
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{
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fpu.io.sfma.valid := Bool(false)
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