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Merge pull request #1060 from freechipsproject/fix-address-format

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Fix address format
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Richard Xia 2017-10-19 10:45:03 -07:00 committed by GitHub
commit 680f3b1620
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/coreplex/BaseCoreplex.scala
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@ -152,7 +152,7 @@ trait HasTilesModuleImp extends LazyModuleImp
abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCoreplexModule(_outer) { abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCoreplexModule(_outer) {
println("Generated Address Map") println("Generated Address Map")
private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1 private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1
private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c %s" private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s"
private def collect(path: List[String], value: ResourceValue): List[(String, ResourceAddress)] = { private def collect(path: List[String], value: ResourceValue): List[(String, ResourceAddress)] = {
value match { value match {
@ -169,11 +169,11 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCor
println(fmt.format( println(fmt.format(
range.base, range.base,
range.base+range.size, range.base+range.size,
if (a) 'A' else ' ',
if (r) 'R' else ' ', if (r) 'R' else ' ',
if (w) 'W' else ' ', if (w) 'W' else ' ',
if (x) 'X' else ' ', if (x) 'X' else ' ',
if (c) 'C' else ' ', if (c) 'C' else ' ',
if (a) 'A' else ' ',
names.mkString(", "))) names.mkString(", ")))
s"""{"base":[${range.base}],"size":[${range.size}],"r":[$r],"w":[$w],"x":[$x],"c":[$c],"a":[$a],"names":[${names.map('"'+_+'"').mkString(",")}]}""" s"""{"base":[${range.base}],"size":[${range.size}],"r":[$r],"w":[$w],"x":[$x],"c":[$c],"a":[$a],"names":[${names.map('"'+_+'"').mkString(",")}]}"""
} }