riscv/rocket-chip
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regmapper RegisterCrossing: safe AsyncQueues are overkill here

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This commit is contained in:
Wesley W. Terpstra 2016-10-14 18:06:24 -07:00
parent ac0bb841da
commit 680a944f07
1 changed files with 6 additions and 3 deletions
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9
src/main/scala/regmapper/RegisterCrossing.scala
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@ -41,7 +41,10 @@ class RegisterCrossingAssertion extends Module {
val slave_reset = Bool(INPUT) val slave_reset = Bool(INPUT)
} }
assert (io.master_bypass || !io.slave_reset) val up = RegInit(Bool(false))
up := !io.slave_reset
assert (io.master_bypass || !up || !io.slave_reset)
} }
// RegField should support connecting to one of these // RegField should support connecting to one of these
@ -88,7 +91,7 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
val io = new RegisterWriteCrossingIO(gen) val io = new RegisterWriteCrossingIO(gen)
// The crossing must only allow one item inflight at a time // The crossing must only allow one item inflight at a time
val control = Module(new BusyRegisterCrossing) val control = Module(new BusyRegisterCrossing)
val crossing = Module(new AsyncQueue(gen, 1, sync)) val crossing = Module(new AsyncQueue(gen, 1, sync, safe=false))
control.clock := io.master_clock control.clock := io.master_clock
control.reset := io.master_reset control.reset := io.master_reset
@ -141,7 +144,7 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
val io = new RegisterReadCrossingIO(gen) val io = new RegisterReadCrossingIO(gen)
// The crossing must only allow one item inflight at a time // The crossing must only allow one item inflight at a time
val control = Module(new BusyRegisterCrossing) val control = Module(new BusyRegisterCrossing)
val crossing = Module(new AsyncQueue(gen, 1, sync)) val crossing = Module(new AsyncQueue(gen, 1, sync, safe=false))
control.clock := io.master_clock control.clock := io.master_clock
control.reset := io.master_reset control.reset := io.master_reset