riscv/rocket-chip
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Stall div/mul writeback until WB slot is free

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This commit is contained in:
Andrew Waterman 2013-08-24 14:40:57 -07:00
parent d1b5076fee
commit 67f80ba4b2
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/dpath.scala
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@ -162,7 +162,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
div.io.req.bits.in2 := ex_rs2 div.io.req.bits.in2 := ex_rs2
div.io.req.bits.tag := ex_reg_waddr div.io.req.bits.tag := ex_reg_waddr
div.io.kill := io.ctrl.div_mul_kill div.io.kill := io.ctrl.div_mul_kill
div.io.resp.ready := Bool(true) div.io.resp.ready := !io.ctrl.mem_wen
io.ctrl.div_mul_rdy := div.io.req.ready io.ctrl.div_mul_rdy := div.io.req.ready
io.fpu.fromint_data := ex_rs1 io.fpu.fromint_data := ex_rs1
@ -249,7 +249,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val mem_ll_wdata = Bits() val mem_ll_wdata = Bits()
mem_ll_wdata := div.io.resp.bits.data mem_ll_wdata := div.io.resp.bits.data
io.ctrl.mem_ll_waddr := div.io.resp.bits.tag io.ctrl.mem_ll_waddr := div.io.resp.bits.tag
io.ctrl.mem_ll_wb := div.io.resp.valid io.ctrl.mem_ll_wb := div.io.resp.valid && !io.ctrl.mem_wen
when (dmem_resp_replay) { when (dmem_resp_replay) {
div.io.resp.ready := Bool(false) div.io.resp.ready := Bool(false)
mem_ll_wdata := io.dmem.resp.bits.data_subword mem_ll_wdata := io.dmem.resp.bits.data_subword