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hopefully fixed last bugs in Bufferless

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This commit is contained in:
Howard Mao 2016-07-04 17:00:27 -07:00
parent a35388bc27
commit 67bac383e3
1 changed files with 7 additions and 3 deletions
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6
uncore/src/main/scala/agents/Bufferless.scala
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@ -42,7 +42,9 @@ class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoheren
allocs = trackerList.map(_.io.alloc.iacq), allocs = trackerList.map(_.io.alloc.iacq),
allocOverride = Some(!irel_vs_iacq_conflict)) allocOverride = Some(!irel_vs_iacq_conflict))
io.outer.acquire.bits.data := io.inner.acquire.bits.data io.outer.acquire.bits.data := io.inner.acquire.bits.data
when (io.oacq().hasData()) {
io.outer.acquire.bits.addr_beat := io.inner.acquire.bits.addr_beat io.outer.acquire.bits.addr_beat := io.inner.acquire.bits.addr_beat
}
// Handle releases, which might be voluntary and might have data // Handle releases, which might be voluntary and might have data
doInputRoutingWithAllocation( doInputRoutingWithAllocation(
@ -50,7 +52,9 @@ class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoheren
outs = trackerList.map(_.io.inner.release), outs = trackerList.map(_.io.inner.release),
allocs = trackerList.map(_.io.alloc.irel)) allocs = trackerList.map(_.io.alloc.irel))
io.outer.release.bits.data := io.inner.release.bits.data io.outer.release.bits.data := io.inner.release.bits.data
when (io.orel().hasData()) {
io.outer.release.bits.addr_beat := io.inner.release.bits.addr_beat io.outer.release.bits.addr_beat := io.inner.release.bits.addr_beat
}
// Wire probe requests and grant reply to clients, finish acks from clients // Wire probe requests and grant reply to clients, finish acks from clients
doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe)) doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
@ -102,7 +106,7 @@ class BufferlessBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
// transaction and (in case of PutBlock) subsequent tail beats // transaction and (in case of PutBlock) subsequent tail beats
val iacq_can_forward = iacq_same_xact && !vol_ognt_counter.pending val iacq_can_forward = iacq_same_xact && !vol_ognt_counter.pending
io.inner.acquire.ready := Mux(io.iacq().hasData(), io.inner.acquire.ready := Mux(io.iacq().hasData(),
state === s_outer_acquire && iacq_can_forward, state === s_outer_acquire && iacq_can_forward && io.outer.acquire.ready,
state === s_idle && io.alloc.iacq.should) state === s_idle && io.alloc.iacq.should)
// Track which clients yet need to be probed and make Probe message // Track which clients yet need to be probed and make Probe message