diplomacy: guess the LazyModule name from the containing class

src/main/scala/diplomacy/LazyModule.scala

@@ -16,7 +16,19 @@ abstract class LazyModule
   LazyModule.stack = this :: LazyModule.stack
   parent.foreach(p => p.children = this :: p.children)
 
-  def name = getClass.getName.split('.').last
+  lazy val className = getClass.getName.split('.').last
+  lazy val valName = parent.flatMap { p =>
+    p.getClass.getMethods.filter { m =>
+      m.getParameterTypes.isEmpty &&
+      !java.lang.reflect.Modifier.isStatic(m.getModifiers) &&
+      classOf[LazyModule].isAssignableFrom(m.getReturnType) &&
+      (m.invoke(p) eq this)
+    }.headOption.map(_.getName)
+  }
+
+  def moduleName = className + valName.map("_" + _).getOrElse("")
+  def instanceName = valName.getOrElse(className)
+  def name = valName.getOrElse(className)
   def line = sourceLine(info)
 
   def module: LazyModuleImp
@@ -91,6 +103,8 @@ abstract class LazyModuleImp(outer: LazyModule) extends Module
   // .module had better not be accessed while LazyModules are still being built!
   require (LazyModule.stack.isEmpty, s"${outer.name}.module was constructed before LazyModule() was run on ${LazyModule.stack.head.name}")
 
-  override def desiredName = outer.name
+  override def desiredName = outer.moduleName
+  suggestName(outer.instanceName)
+
   outer.instantiate()
 }

src/main/scala/diplomacy/Nodes.scala

@@ -42,7 +42,8 @@ abstract class BaseNode
   val index = lazyModule.nodes.size
   lazyModule.nodes = this :: lazyModule.nodes
 
-  def name = lazyModule.name + "." + getClass.getName.split('.').last
+  def nodename = getClass.getName.split('.').last
+  def name = lazyModule.name + "." + nodename
   def omitGraphML = outputs.isEmpty && inputs.isEmpty
 
   protected[diplomacy] def outputs: Seq[BaseNode]

src/main/scala/rocketchip/Periphery.scala

@@ -330,9 +330,8 @@ trait PeripheryBootROM extends LazyModule with HasPeripheryParameters {
 
   val address = 0x1000
   val size = 0x1000
-  val rom = LazyModule(new TLROM(address, size, GenerateBootROM(p, address), true, peripheryBusConfig.beatBytes)
-                       { override def name = "bootrom" })
-  rom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+  val bootrom = LazyModule(new TLROM(address, size, GenerateBootROM(p, address), true, peripheryBusConfig.beatBytes))
+  bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
 }
 
 trait PeripheryBootROMBundle {

src/main/scala/uncore/devices/Prci.scala

@@ -90,6 +90,3 @@ class CoreplexLocalInterrupter(c: CoreplexLocalInterrupterConfig)(implicit val p
   extends TLRegisterRouter(c.address, 0, c.size, 0, c.beatBytes, false)(
   new TLRegBundle((c, p), _)    with CoreplexLocalInterrupterBundle)(
   new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule)
-{
-  override def name = "clint" // defaul is "CoreplexLocalInterrupter"
-}