riscv/rocket-chip
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diplomacy: guess the LazyModule name from the containing class

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Wesley W. Terpstra 2016-10-14 15:11:13 -07:00 committed by mwachs5
parent 4d50733548
commit 67ab27f5a5
4 changed files with 20 additions and 9 deletions
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18
src/main/scala/diplomacy/LazyModule.scala
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@ -16,7 +16,19 @@ abstract class LazyModule
LazyModule.stack = this :: LazyModule.stack LazyModule.stack = this :: LazyModule.stack
parent.foreach(p => p.children = this :: p.children) parent.foreach(p => p.children = this :: p.children)
def name = getClass.getName.split('.').last lazy val className = getClass.getName.split('.').last
lazy val valName = parent.flatMap { p =>
p.getClass.getMethods.filter { m =>
m.getParameterTypes.isEmpty &&
!java.lang.reflect.Modifier.isStatic(m.getModifiers) &&
classOf[LazyModule].isAssignableFrom(m.getReturnType) &&
(m.invoke(p) eq this)
}.headOption.map(_.getName)
}
def moduleName = className + valName.map("_" + _).getOrElse("")
def instanceName = valName.getOrElse(className)
def name = valName.getOrElse(className)
def line = sourceLine(info) def line = sourceLine(info)
def module: LazyModuleImp def module: LazyModuleImp
@ -91,6 +103,8 @@ abstract class LazyModuleImp(outer: LazyModule) extends Module
// .module had better not be accessed while LazyModules are still being built! // .module had better not be accessed while LazyModules are still being built!
require (LazyModule.stack.isEmpty, s"${outer.name}.module was constructed before LazyModule() was run on ${LazyModule.stack.head.name}") require (LazyModule.stack.isEmpty, s"${outer.name}.module was constructed before LazyModule() was run on ${LazyModule.stack.head.name}")
override def desiredName = outer.name override def desiredName = outer.moduleName
suggestName(outer.instanceName)
outer.instantiate() outer.instantiate()
} }

3
src/main/scala/diplomacy/Nodes.scala
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@ -42,7 +42,8 @@ abstract class BaseNode
val index = lazyModule.nodes.size val index = lazyModule.nodes.size
lazyModule.nodes = this :: lazyModule.nodes lazyModule.nodes = this :: lazyModule.nodes
def name = lazyModule.name + "." + getClass.getName.split('.').last def nodename = getClass.getName.split('.').last
def name = lazyModule.name + "." + nodename
def omitGraphML = outputs.isEmpty && inputs.isEmpty def omitGraphML = outputs.isEmpty && inputs.isEmpty
protected[diplomacy] def outputs: Seq[BaseNode] protected[diplomacy] def outputs: Seq[BaseNode]

5
src/main/scala/rocketchip/Periphery.scala
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@ -330,9 +330,8 @@ trait PeripheryBootROM extends LazyModule with HasPeripheryParameters {
val address = 0x1000 val address = 0x1000
val size = 0x1000 val size = 0x1000
val rom = LazyModule(new TLROM(address, size, GenerateBootROM(p, address), true, peripheryBusConfig.beatBytes) val bootrom = LazyModule(new TLROM(address, size, GenerateBootROM(p, address), true, peripheryBusConfig.beatBytes))
{ override def name = "bootrom" }) bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
rom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
} }
trait PeripheryBootROMBundle { trait PeripheryBootROMBundle {

3
src/main/scala/uncore/devices/Prci.scala
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@ -90,6 +90,3 @@ class CoreplexLocalInterrupter(c: CoreplexLocalInterrupterConfig)(implicit val p
extends TLRegisterRouter(c.address, 0, c.size, 0, c.beatBytes, false)( extends TLRegisterRouter(c.address, 0, c.size, 0, c.beatBytes, false)(
new TLRegBundle((c, p), _) with CoreplexLocalInterrupterBundle)( new TLRegBundle((c, p), _) with CoreplexLocalInterrupterBundle)(
new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule) new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule)
{
override def name = "clint" // defaul is "CoreplexLocalInterrupter"
}