fix bugs from adding ComparatorSource backpressure
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d435bb4185
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676a536706
@ -69,13 +69,10 @@ class ComparatorSource(implicit val p: Parameters) extends Module
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}
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}
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// Output exactly nOperations of Acquires
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// Output exactly nOperations of Acquires
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val counter = RegInit(UInt(nOperations))
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val finished = RegInit(Bool(false))
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val finished = RegInit(Bool(false))
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val valid = RegInit(Bool(false))
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val valid = RegInit(Bool(false))
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valid := Bool(true)
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valid := Bool(true)
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counter := counter - (!finished && valid).asUInt
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when (counter === UInt(1)) { finished := Bool(true) }
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io.finished := finished
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io.finished := finished
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io.out.valid := !finished && valid
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io.out.valid := !finished && valid
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@ -148,15 +145,13 @@ class ComparatorSource(implicit val p: Parameters) extends Module
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UInt("b101") -> getPrefetch,
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UInt("b101") -> getPrefetch,
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UInt("b110") -> putPrefetch)))
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UInt("b110") -> putPrefetch)))
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when (!done_wipe && valid) {
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wipe_addr_block := wipe_addr_block + UInt(1)
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}
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val idx = Reg(init = UInt(0, log2Up(nOperations)))
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val idx = Reg(init = UInt(0, log2Up(nOperations)))
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when (io.out.fire()) {
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when (io.out.fire()) {
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when (idx === UInt(nOperations - 1)) { finished := Bool(true) }
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when (!done_wipe) {
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when (!done_wipe) {
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printf("[acq %d]: PutBlock(addr_block = %x, data = %x)\n",
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printf("[acq %d]: PutBlock(addr_block = %x, data = %x)\n",
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idx, wipe_addr_block, data)
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idx, wipe_addr_block, data)
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wipe_addr_block := wipe_addr_block + UInt(1)
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} .otherwise {
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} .otherwise {
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switch (a_type_sel) {
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switch (a_type_sel) {
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is (UInt("b000")) {
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is (UInt("b000")) {
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@ -343,7 +338,6 @@ class ComparatorSink(implicit val p: Parameters) extends Module
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}
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}
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}
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}
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when (all_valid) {
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when (all_valid) {
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// Skip the results generated by the block wiping
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when (base.hasData()) {
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when (base.hasData()) {
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printf("[gnt %d]: g_type = %x, addr_beat = %x, data = %x\n",
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printf("[gnt %d]: g_type = %x, addr_beat = %x, data = %x\n",
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idx, base.g_type, base.addr_beat, base.data)
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idx, base.g_type, base.addr_beat, base.data)
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