From 676974281ab5d9af2bb7ec7d44e1ac82759b6e09 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 3 Mar 2017 02:54:48 -0800
Subject: [PATCH] rocket: describe dcache scratchpad as memory

---
 src/main/scala/rocket/ScratchpadSlavePort.scala | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala
index 7bcc7a7f..3c5a9794 100644
--- a/src/main/scala/rocket/ScratchpadSlavePort.scala
+++ b/src/main/scala/rocket/ScratchpadSlavePort.scala
@@ -15,9 +15,11 @@ import util._
 
 class ScratchpadSlavePort(sizeBytes: Int)(implicit p: Parameters) extends LazyModule
     with HasCoreParameters {
+  val device = new MemoryDevice
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = List(AddressSet(0x80000000L, BigInt(sizeBytes-1))),
+      resources          = device.reg,
       regionType         = RegionType.UNCACHED,
       executable         = true,
       supportsArithmetic = if (usingAtomics) TransferSizes(1, coreDataBytes) else TransferSizes.none,