riscv/rocket-chip
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Add cover for a1ebe6da4d

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This commit is contained in:
Andrew Waterman 2017-12-07 20:47:31 -08:00
parent a1ebe6da4d
commit 676110bc1f
1 changed files with 6 additions and 0 deletions
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6
src/main/scala/rocket/Frontend.scala
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@ -12,6 +12,8 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import chisel3.internal.sourceinfo.SourceInfo
class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
val pc = UInt(width = vaddrBitsExtended)
@ -208,6 +210,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
btb.io.flush := true
fq.io.enq.bits.replay := true
wrong_path := true
ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path")
}
when (!prevTaken) {
@ -298,6 +301,9 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
io.errors := icache.io.errors
def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1))
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, s"FRONTEND_$label", "Rocket;;" + desc)
}
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */