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add support for AXI streaming protocol

This commit is contained in:
Howard Mao 2016-01-05 20:04:49 -08:00
parent c57639b23f
commit 673f73b051
2 changed files with 101 additions and 5 deletions

View File

@ -113,14 +113,29 @@ class NastiReadDataChannel(implicit p: Parameters) extends NastiResponseChannel(
val user = UInt(width = nastiRUserBits) val user = UInt(width = nastiRUserBits)
} }
object NastiConstants {
val BURST_FIXED = UInt("b00")
val BURST_INCR = UInt("b01")
val BURST_WRAP = UInt("b10")
val RESP_OKAY = UInt("b00")
val RESP_EXOKAY = UInt("b01")
val RESP_SLVERR = UInt("b10")
val RESP_DECERR = UInt("b11")
}
import NastiConstants._
object NastiWriteAddressChannel { object NastiWriteAddressChannel {
def apply(id: UInt, addr: UInt, size: UInt, len: UInt = UInt(0))(implicit p: Parameters) = { def apply(id: UInt, addr: UInt, size: UInt,
len: UInt = UInt(0), burst: UInt = BURST_INCR)
(implicit p: Parameters) = {
val aw = Wire(new NastiWriteAddressChannel) val aw = Wire(new NastiWriteAddressChannel)
aw.id := id aw.id := id
aw.addr := addr aw.addr := addr
aw.len := len aw.len := len
aw.size := size aw.size := size
aw.burst := UInt("b01") aw.burst := burst
aw.lock := Bool(false) aw.lock := Bool(false)
aw.cache := UInt("b0000") aw.cache := UInt("b0000")
aw.prot := UInt("b000") aw.prot := UInt("b000")
@ -132,13 +147,15 @@ object NastiWriteAddressChannel {
} }
object NastiReadAddressChannel { object NastiReadAddressChannel {
def apply(id: UInt, addr: UInt, size: UInt, len: UInt = UInt(0))(implicit p: Parameters) = { def apply(id: UInt, addr: UInt, size: UInt,
len: UInt = UInt(0), burst: UInt = BURST_INCR)
(implicit p: Parameters) = {
val ar = Wire(new NastiReadAddressChannel) val ar = Wire(new NastiReadAddressChannel)
ar.id := id ar.id := id
ar.addr := addr ar.addr := addr
ar.len := len ar.len := len
ar.size := size ar.size := size
ar.burst := UInt("b01") ar.burst := burst
ar.lock := Bool(false) ar.lock := Bool(false)
ar.cache := UInt(0) ar.cache := UInt(0)
ar.prot := UInt(0) ar.prot := UInt(0)
@ -333,7 +350,7 @@ class NastiErrorSlave(implicit p: Parameters) extends NastiModule {
io.r.valid := r_queue.io.deq.valid && responding io.r.valid := r_queue.io.deq.valid && responding
io.r.bits.id := r_queue.io.deq.bits.id io.r.bits.id := r_queue.io.deq.bits.id
io.r.bits.data := UInt(0) io.r.bits.data := UInt(0)
io.r.bits.resp := Bits("b11") io.r.bits.resp := RESP_DECERR
io.r.bits.last := beats_left === UInt(0) io.r.bits.last := beats_left === UInt(0)
r_queue.io.deq.ready := io.r.fire() && io.r.bits.last r_queue.io.deq.ready := io.r.fire() && io.r.bits.last

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@ -0,0 +1,79 @@
package junctions
import Chisel._
import NastiConstants._
import cde.Parameters
class StreamChannel(w: Int) extends Bundle {
val data = UInt(width = w)
val last = Bool()
override def cloneType = new StreamChannel(w).asInstanceOf[this.type]
}
class StreamIO(w: Int) extends Bundle {
val out = Decoupled(new StreamChannel(w))
val in = Decoupled(new StreamChannel(w)).flip
override def cloneType = new StreamIO(w).asInstanceOf[this.type]
}
class NastiIOStreamIOConverter(w: Int)(implicit p: Parameters) extends Module {
val io = new Bundle {
val nasti = (new NastiIO).flip
val stream = new StreamIO(w)
}
val streamSize = UInt(log2Up(w / 8))
assert(!io.nasti.ar.valid || io.nasti.ar.bits.size === streamSize,
"read channel wrong size on stream")
assert(!io.nasti.ar.valid || io.nasti.ar.bits.burst === BURST_FIXED,
"read channel wrong burst type on stream")
assert(!io.nasti.aw.valid || io.nasti.aw.bits.size === streamSize,
"write channel wrong size on stream")
assert(!io.nasti.aw.valid || io.nasti.aw.bits.burst === BURST_FIXED,
"write channel wrong burst type on stream")
val read_id = Reg(io.nasti.ar.bits.id)
val reading = Reg(init = Bool(false))
io.nasti.ar.ready := !reading
io.nasti.r.valid := reading && io.stream.in.valid
io.nasti.r.bits := io.stream.in.bits
io.nasti.r.bits.resp := UInt(0)
io.nasti.r.bits.id := read_id
io.stream.in.ready := reading && io.nasti.r.ready
when (io.nasti.ar.fire()) {
read_id := io.nasti.ar.bits.id
reading := Bool(true)
}
when (io.nasti.r.fire() && io.nasti.r.bits.last) {
reading := Bool(false)
}
val write_id = Reg(io.nasti.aw.bits.id)
val writing = Reg(init = Bool(false))
val write_resp = Reg(init = Bool(false))
io.nasti.aw.ready := !writing && !write_resp
io.nasti.w.ready := writing && io.stream.out.ready
io.stream.out.valid := writing && io.nasti.w.valid
io.stream.out.bits := io.nasti.w.bits
io.nasti.b.valid := write_resp
io.nasti.b.bits.resp := UInt(0)
io.nasti.b.bits.id := write_id
when (io.nasti.aw.fire()) {
write_id := io.nasti.aw.bits.id
writing := Bool(true)
}
when (io.nasti.w.fire() && io.nasti.w.bits.last) {
writing := Bool(false)
write_resp := Bool(true)
}
when (io.nasti.b.fire()) { write_resp := Bool(false) }
}