riscv/rocket-chip
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Merge branch 'master' into unittest-config

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Henry Cook authored and GitHub committed 2016-09-22 16:20:53 -07:00
2 parents 1e54820f8c 06d8140b61
commit 673efb400d
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src/main/scala/rocketchip/BaseTop.scala
+1 -1
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@@ -49,7 +49,7 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
peripheryBus.node := TLBuffer(TLWidthWidget(TLHintHandler(legacy.node), legacy.tlDataBytes))
peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
}
abstract class BaseTopBundle(val p: Parameters) extends Bundle {