tilelink2 RegisterRouter: support new TL2 interrupts

2016-09-08 15:17:30 -07:00
parent 23e896ed5d
commit 66f58cf2d0
3 changed files with 30 additions and 11 deletions
--- a/src/main/scala/uncore/tilelink2/RegField.scala
+++ b/src/main/scala/uncore/tilelink2/RegField.scala
@ -86,6 +86,7 @@ object RegField
 trait HasRegMap
 {
  def regmap(mapping: RegField.Map*): Unit
+  val interrupts: Vec[Bool]
 }

 // See GPIO.scala for an example of how to use regmap