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tilelink2 RegisterRouter: support new TL2 interrupts

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Wesley W. Terpstra committed 2016-09-08 15:25:50 -07:00
1 parent 23e896ed5d
commit 66f58cf2d0
3 files changed
+30 -11
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src/main/scala/uncore/tilelink2/RegField.scala
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@@ -86,6 +86,7 @@ object RegField
trait HasRegMap
{
def regmap(mapping: RegField.Map*): Unit
val interrupts: Vec[Bool]
}
// See GPIO.scala for an example of how to use regmap