riscv/rocket-chip
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Correct Debug + WFI Interactions

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1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
This commit is contained in:
Megan Wachs 2017-06-27 13:31:29 -07:00
parent c9cfe46604
commit 665c2a349c
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/CSR.scala
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@ -505,8 +505,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val exception = insn_call || insn_break || io.exception val exception = insn_call || insn_break || io.exception
assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive")
when (insn_wfi) { reg_wfi := true } when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true }
when (pending_interrupts.orR || exception) { reg_wfi := false } when (pending_interrupts.orR || exception || reg_dcsr.debugint) { reg_wfi := false }
assert(!reg_wfi || io.retire === UInt(0)) assert(!reg_wfi || io.retire === UInt(0))
when (io.retire(0) || exception) { reg_singleStepped := true } when (io.retire(0) || exception) { reg_singleStepped := true }