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rom+sram: add a compatible field

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This commit is contained in:
Wesley W. Terpstra 2017-06-28 15:41:20 -07:00
parent ca3030cba3
commit 66489ffa13
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/uncore/devices/Rom.scala
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@ -13,7 +13,7 @@ import uncore.util._
import config._ import config._
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4, class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
resources: Seq[Resource] = new SimpleDevice("rom", Nil).reg("mem"))(implicit p: Parameters) extends LazyModule resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
{ {
val node = TLManagerNode(beatBytes, TLManagerParameters ( val node = TLManagerNode(beatBytes, TLManagerParameters (

2
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -10,7 +10,7 @@ import util._
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule
{ {
val device = name.map(new SimpleDevice(_, Nil)).getOrElse(new MemoryDevice) val device = name.map(new SimpleDevice(_, Seq("sifive,sram0"))).getOrElse(new MemoryDevice)
val node = TLManagerNode(Seq(TLManagerPortParameters( val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters( Seq(TLManagerParameters(
address = List(address), address = List(address),