riscv/rocket-chip
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merge I$, ITLB, BTB into Frontend

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This commit is contained in:
Andrew Waterman
2012-10-09 21:35:03 -07:00
parent fcd69dba98
commit 661f8e635b
15 changed files with 946 additions and 1143 deletions
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4
rocket/src/main/scala/tile.scala
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@ -13,7 +13,7 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
}
val cpu = new rocketProc
val icache = new rocketICache(128, 4, co) // 128 sets x 4 ways (32KB)
val icache = new Frontend(ICacheConfig(co, 128, 4)) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache(co)
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
@ -31,7 +31,7 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
if (HAVE_VEC)
{
val vicache = new rocketICache(128, 1, co) // 128 sets x 1 ways (8KB)
val vicache = new Frontend(ICacheConfig(co, 128, 1)) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu
}