merge I$, ITLB, BTB into Frontend
This commit is contained in:
Andrew Waterman
@ -6,172 +6,249 @@ import Constants._;
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import scala.math._;
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import uncore._
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// interface between I$ and pipeline/ITLB (32 bits wide)
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class ioImem extends Bundle
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case class ICacheConfig(co: CoherencePolicyWithUncached, sets: Int, assoc: Int, parity: Boolean = false)
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{
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val invalidate = Bool(INPUT);
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val itlb_miss = Bool(INPUT);
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val req_val = Bool(INPUT);
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val req_idx = Bits(INPUT, PGIDX_BITS);
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val req_ppn = Bits(INPUT, PPN_BITS);
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val resp_data = Bits(OUTPUT, 32);
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val resp_val = Bool(OUTPUT);
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val w = 1
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val ibytes = INST_BITS/8
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val dm = assoc == 1
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val lines = sets * assoc
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val databits = MEM_DATA_BITS
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val datawidth = databits + (if (parity) 1 else 0)
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val idxbits = log2Up(sets)
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val offbits = OFFSET_BITS
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val untagbits = idxbits + offbits
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val tagbits = PADDR_BITS - untagbits
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val tagwidth = tagbits + (if (parity) 1 else 0)
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require(isPow2(sets) && isPow2(assoc))
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require(isPow2(w) && isPow2(ibytes))
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require(PGIDX_BITS >= untagbits)
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}
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class ioRocketICache extends Bundle()
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{
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val cpu = new ioImem();
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val mem = new ioUncachedRequestor
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class FrontendReq extends Bundle {
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val pc = UFix(width = VADDR_BITS+1)
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val status = Bits(width = 32)
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val invalidate = Bool()
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val invalidateTLB = Bool()
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val mispredict = Bool()
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val taken = Bool()
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val currentpc = UFix(width = VADDR_BITS+1)
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}
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// basic direct mapped instruction cache
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// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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// parameters :
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// lines = # cache lines
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class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) extends Component
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class FrontendResp extends Bundle {
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val pc = UFix(width = VADDR_BITS+1) // ID stage PC
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val data = Bits(width = INST_BITS)
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val taken = Bool()
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val xcpt_ma = Bool()
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val xcpt_if = Bool()
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}
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class IOCPUFrontend extends Bundle {
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val req = new PipeIO()(new FrontendReq)
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val resp = new FIFOIO()(new FrontendResp).flip
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val ptw = new IOTLBPTW().flip
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}
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class Frontend(c: ICacheConfig) extends Component
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{
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val io = new ioRocketICache();
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val lines = sets * assoc;
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val addrbits = PADDR_BITS;
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val indexbits = log2Up(sets);
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val offsetbits = OFFSET_BITS;
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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val tagbits = addrbits-taglsb;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val databits = 32;
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val offsetlsb = log2Up(databits/8);
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val rf_cnt_bits = log2Up(REFILL_CYCLES);
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require(PGIDX_BITS >= taglsb); // virtually-indexed, physically-tagged constraint
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require(isPow2(sets) && isPow2(assoc));
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val io = new Bundle {
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val cpu = new IOCPUFrontend().flip
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val mem = new ioUncachedRequestor
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}
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val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() };
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val state = Reg(resetVal = s_reset);
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val btb = new rocketDpathBTB(BTB_ENTRIES)
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val icache = new ICache(c)
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val tlb = new TLB(ITLB_ENTRIES)
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val s1_pc = Reg() { UFix() }
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val s2_valid = Reg(resetVal = Bool(true))
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val s2_pc = Reg(resetVal = UFix(START_ADDR))
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val s2_btb_hit = Reg(resetVal = Bool(false))
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val s2_xcpt_if = Reg(resetVal = Bool(false))
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val btbTarget = Cat(btb.io.target(VADDR_BITS-1), btb.io.target)
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val pcp4_0 = s1_pc + UFix(c.ibytes)
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val pcp4 = Cat(s1_pc(VADDR_BITS-1) & pcp4_0(VADDR_BITS-1), pcp4_0(VADDR_BITS-1,0))
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val icmiss = s2_valid && !icache.io.resp.valid
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val npc = Mux(icmiss, s2_pc, Mux(btb.io.hit, btbTarget, pcp4)).toUFix
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val stall = !io.cpu.resp.ready
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when (!stall) {
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s1_pc := npc
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s2_valid := !icmiss
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s2_pc := s1_pc
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s2_btb_hit := btb.io.hit
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s2_xcpt_if := tlb.io.resp.xcpt_if
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}
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when (io.cpu.req.valid) {
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s1_pc := io.cpu.req.bits.pc
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s2_valid := Bool(false)
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}
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btb.io.current_pc := s1_pc
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btb.io.wen := io.cpu.req.bits.mispredict
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btb.io.clr := !io.cpu.req.bits.taken
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btb.io.correct_pc := io.cpu.req.bits.currentpc
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btb.io.correct_target := io.cpu.req.bits.pc
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btb.io.invalidate := io.cpu.req.bits.invalidate || io.cpu.req.bits.invalidateTLB
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tlb.io.ptw <> io.cpu.ptw
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tlb.io.req.valid := !stall && !icmiss
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tlb.io.req.bits.vpn := s1_pc >> UFix(PGIDX_BITS)
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tlb.io.req.bits.status := io.cpu.req.bits.status
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tlb.io.req.bits.asid := UFix(0)
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tlb.io.req.bits.invalidate := io.cpu.req.bits.invalidateTLB
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tlb.io.req.bits.instruction := Bool(true)
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icache.io.mem <> io.mem
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icache.io.req.valid := !stall
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icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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icache.io.req.bits.invalidate := io.cpu.req.bits.invalidate
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icache.io.req.bits.ppn := tlb.io.resp.ppn
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icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss
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icache.io.resp.ready := io.cpu.resp.ready
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
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io.cpu.resp.bits.pc := s2_pc
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io.cpu.resp.bits.data := icache.io.resp.bits.data
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io.cpu.resp.bits.taken := s2_btb_hit
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io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(c.ibytes)-1,0) != UFix(0)
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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}
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class ICache(c: ICacheConfig) extends Component
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{
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val io = new Bundle {
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val req = new PipeIO()(new Bundle {
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val idx = UFix(width = PGIDX_BITS)
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val invalidate = Bool()
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val ppn = UFix(width = PPN_BITS) // delayed one cycle
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val kill = Bool() // delayed one cycle
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}).flip
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val resp = new FIFOIO()(new Bundle {
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val data = Bits(width = INST_BITS)
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val datablock = Bits(width = c.databits)
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})
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val mem = new ioUncachedRequestor
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}
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val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(4) { UFix() }
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val state = Reg(resetVal = s_ready)
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val invalidated = Reg() { Bool() }
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val r_cpu_req_idx = Reg { Bits() }
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val r_cpu_req_ppn = Reg { Bits() }
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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val stall = !io.resp.ready
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val rdy = Bool()
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val tag_hit = Bool()
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when (io.cpu.req_val && rdy) {
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r_cpu_req_val := Bool(true)
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r_cpu_req_idx := io.cpu.req_idx
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}
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.otherwise {
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r_cpu_req_val := Bool(false)
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}
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when (state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss) {
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r_cpu_req_ppn := io.cpu.req_ppn
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val s2_valid = Reg(resetVal = Bool(false))
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val s2_addr = Reg { UFix(width = PADDR_BITS) }
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val s1_valid = Reg(resetVal = Bool(false))
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val s1_pgoff = Reg() { UFix(width = PGIDX_BITS) }
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val s0_valid = io.req.valid && rdy || s1_valid && stall && !io.req.bits.kill
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val s0_pgoff = Mux(io.req.valid, io.req.bits.idx, s1_pgoff)
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s1_valid := s0_valid
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when (io.req.valid && rdy) {
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s1_pgoff := s0_pgoff
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}
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val r_cpu_hit_addr = Cat(io.cpu.req_ppn, r_cpu_req_idx)
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val r_cpu_hit_tag = r_cpu_hit_addr(tagmsb,taglsb)
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val r_cpu_miss_addr = Cat(r_cpu_req_ppn, r_cpu_req_idx)
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val r_cpu_miss_tag = r_cpu_miss_addr(tagmsb,taglsb)
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// refill counter
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val refill_count = Reg(resetVal = UFix(0, rf_cnt_bits));
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when (io.mem.xact_rep.valid) {
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refill_count := refill_count + UFix(1);
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s2_valid := s1_valid && rdy && !io.req.bits.kill || stall
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when (s1_valid && rdy && !stall) {
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s2_addr := Cat(io.req.bits.ppn, s1_pgoff).toUFix
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}
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val refill_done = io.mem.xact_rep.valid && refill_count.andR
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val repl_way = if (assoc == 1) UFix(0) else LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2Up(assoc)-1,0)
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val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2Up(databits))).toUFix
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val tag_we = refill_done
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val tag_addr =
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Mux((state === s_refill), r_cpu_req_idx(indexmsb,indexlsb),
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io.cpu.req_idx(indexmsb,indexlsb)).toUFix;
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val data_addr =
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(indexmsb,offsetbits), refill_count),
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io.cpu.req_idx(indexmsb, offsetbits-rf_cnt_bits)).toUFix;
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val s2_tag = s2_addr(c.tagbits+c.untagbits-1,c.untagbits)
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val s2_idx = s2_addr(c.untagbits-1,c.offbits)
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val s2_offset = s2_addr(c.offbits-1,0)
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val s2_any_tag_hit = Bool()
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val s2_hit = s2_valid && s2_any_tag_hit
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val s2_miss = s2_valid && !s2_any_tag_hit
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rdy := state === s_ready && !s2_miss
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val tag_array = Mem(sets, seqRead = true) { Bits(width = tagbits*assoc) }
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val (rf_cnt, refill_done) = Counter(io.mem.xact_rep.valid, REFILL_CYCLES)
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val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)
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val tag_array = Mem(c.sets, seqRead = true) { Bits(width = c.tagwidth*c.assoc) }
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val tag_rdata = Reg() { Bits() }
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when (tag_we) {
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tag_array.write(tag_addr, Fill(assoc, r_cpu_miss_tag), FillInterleaved(tagbits, if (assoc > 1) UFixToOH(repl_way) else Bits(1)))
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}.otherwise {
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tag_rdata := tag_array(tag_addr)
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when (refill_done) {
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val wmask = FillInterleaved(c.tagwidth, if (c.dm) Bits(1) else UFixToOH(repl_way))
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val tag = Cat(if (c.parity) s2_tag.xorR else null, s2_tag)
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tag_array.write(s2_idx, Fill(c.assoc, tag), wmask)
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}.elsewhen (s0_valid) {
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tag_rdata := tag_array(s0_pgoff(c.untagbits-1,c.offbits))
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}
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val vb_array = Reg(resetVal = Bits(0, lines))
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when (io.cpu.invalidate) {
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val vb_array = Reg(resetVal = Bits(0, c.lines))
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when (refill_done && !invalidated) {
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vb_array := vb_array.bitSet(Cat(repl_way, s2_idx), Bool(true))
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}
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when (io.req.bits.invalidate) {
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vb_array := Bits(0)
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}.elsewhen (tag_we) {
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vb_array := vb_array.bitSet(Cat(r_cpu_req_idx(indexmsb,indexlsb), if (assoc > 1) repl_way else null), !invalidated)
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invalidated := Bool(true)
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}
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val s2_disparity = Vec(c.assoc) { Bool() }
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for (i <- 0 until c.assoc)
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when (s2_valid && s2_disparity(i)) { vb_array := vb_array.bitSet(Cat(UFix(i), s2_idx), Bool(false)) }
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val data_mux = (new Mux1H(assoc)){Bits(width = databits)}
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var any_hit = Bool(false)
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for (i <- 0 until assoc)
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{
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val valid = vb_array(Cat(r_cpu_req_idx(indexmsb,indexlsb), if (assoc > 1) UFix(i, log2Up(assoc)) else null))
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val hit = valid && tag_rdata(tagbits*(i+1)-1, tagbits*i) === r_cpu_hit_addr(tagmsb,taglsb)
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// data array
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val data_array = Mem(sets*REFILL_CYCLES, seqRead = true){ io.mem.xact_rep.bits.data.clone }
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val data_out = Reg(){ io.mem.xact_rep.bits.data.clone }
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when (io.mem.xact_rep.valid && repl_way === UFix(i)) { data_array(data_addr) := io.mem.xact_rep.bits.data }
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.otherwise { data_out := data_array(data_addr) }
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data_mux.io.sel(i) := hit
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data_mux.io.in(i) := (data_out >> word_shift)(databits-1,0);
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any_hit = any_hit || hit
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val s2_tag_hit = Vec(c.assoc) { Bool() }
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val s2_data_disparity = Vec(c.assoc) { Bool() }
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for (i <- 0 until c.assoc) {
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val s1_vb = vb_array(Cat(UFix(i), s1_pgoff(c.untagbits-1,c.offbits))).toBool
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val s2_vb = Reg() { Bool() }
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val s2_tag_out = Reg() { Bits() }
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when (s1_valid && rdy && !stall) {
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s2_vb := s1_vb
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s2_tag_out := tag_rdata(c.tagwidth*(i+1)-1, c.tagwidth*i)
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}
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s2_tag_hit(i) := s2_vb && s2_tag_out(c.tagbits-1,0) === s2_tag
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s2_disparity(i) := Bool(c.parity) && s2_vb && (s2_tag_out.xorR || s2_data_disparity(i))
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}
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tag_hit := any_hit
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s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
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val s2_dout = Vec(c.assoc) { Reg() { Bits(width = c.databits) } }
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for (i <- 0 until c.assoc) {
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val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.datawidth) }
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val s1_dout = Reg(){ Bits() }
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when (io.mem.xact_rep.valid && repl_way === UFix(i)) {
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val d = io.mem.xact_rep.bits.data
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val wdata = if (c.parity) Cat(d.xorR, d) else d
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data_array(Cat(s2_idx,rf_cnt)) := wdata
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}.elsewhen (s0_valid) {
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s1_dout := data_array(s0_pgoff(c.untagbits-1,c.offbits-rf_cnt.getWidth))
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}
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when (s1_valid && rdy && !stall) { s2_dout(i) := s1_dout }
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s2_data_disparity(i) := s2_dout(i).xorR
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}
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val s2_dout_word = s2_dout.map(x => (x >> Cat(s2_offset(log2Up(c.databits/8)-1,log2Up(c.ibytes)), Bits(0,log2Up(c.ibytes*8))))(c.ibytes*8-1,0))
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io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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val finish_q = (new Queue(1)) { new TransactionFinish }
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finish_q.io.enq.valid := refill_done && io.mem.xact_rep.bits.require_ack
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finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
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// output signals
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io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_hit;
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rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
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io.cpu.resp_data := data_mux.io.out
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io.resp.valid := s2_hit
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io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
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io.mem.xact_init.bits := co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
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io.mem.xact_init.bits := c.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
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io.mem.xact_finish <> finish_q.io.deq
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// control state machine
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when (io.cpu.invalidate) {
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invalidated := Bool(true)
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}
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switch (state) {
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is (s_reset) {
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state := s_ready;
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}
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is (s_ready) {
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when (r_cpu_req_val && !tag_hit && !io.cpu.itlb_miss) {
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state := s_request;
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}
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when (s2_miss) { state := s_request }
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invalidated := Bool(false)
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}
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is (s_request)
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{
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when (io.mem.xact_init.ready && finish_q.io.enq.ready) {
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state := s_refill_wait;
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}
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is (s_request) {
|
||||
when (io.mem.xact_init.ready && finish_q.io.enq.ready) { state := s_refill_wait }
|
||||
}
|
||||
is (s_refill_wait) {
|
||||
when (io.mem.xact_abort.valid) {
|
||||
state := s_request
|
||||
}
|
||||
when (io.mem.xact_rep.valid) {
|
||||
state := s_refill;
|
||||
}
|
||||
when (io.mem.xact_abort.valid) { state := s_request }
|
||||
when (io.mem.xact_rep.valid) { state := s_refill }
|
||||
}
|
||||
is (s_refill) {
|
||||
when (refill_done) {
|
||||
state := s_ready;
|
||||
}
|
||||
when (refill_done) { state := s_ready }
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user