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coreplex: TileMasterPortParams inject adapters into SBus

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This commit is contained in:
Henry Cook
2017-10-10 15:02:50 -07:00
parent 9026646459
commit 660355004e
3 changed files with 80 additions and 33 deletions
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44
src/main/scala/coreplex/SystemBus.scala
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@ -27,9 +27,6 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
protected def inwardSplitNode: TLInwardNode = master_splitter.node
protected def outwardSplitNode: TLOutwardNode = master_splitter.node
private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
tile_fixer.suggestName(s"${busName}_tile_TLFIFOFixer")
master_splitter.node :=* tile_fixer.node
private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
port_fixer.suggestName(s"${busName}_port_TLFIFOFixer")
@ -55,34 +52,33 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def fromFrontBus: TLInwardNode = master_splitter.node
def fromSyncTiles(params: BufferParams, port: TilePortParams, name: Option[String] = None): TLInwardNode = {
val tile_buf = LazyModule(new TLBuffer(params))
name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") }
val (in, out) = bufferChain(port.addBuffers, name = name)
def fromSyncTiles(params: BufferParams, adapt: () => TLNodeChain, name: Option[String] = None): TLInwardNode = {
val adapters = adapt() // wanted to be called inside SystemBus scope
val tile_sink = LazyModule(new TLBuffer(params))
name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLBuffer") }
tile_fixer.node :=* out
in :=* tile_buf.node
tile_buf.node
}
def fromRationalTiles(dir: RationalDirection, port: TilePortParams, name: Option[String] = None): TLRationalInwardNode = {
// TODO val tile_blocker = port.blockerCtrlAddr.map(a => LazyModule(new BusBlocker(BusBlockerParams(a, , ))))
val tile_sink = LazyModule(new TLRationalCrossingSink(direction = dir))
name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
val (in, out) = bufferChain(port.addBuffers, name = name)
tile_fixer.node :=* out
in :=* tile_sink.node
adapters.in :=* tile_sink.node
master_splitter.node :=* adapters.out
tile_sink.node
}
def fromAsyncTiles(depth: Int, sync: Int, port: TilePortParams, name: Option[String] = None): TLAsyncInwardNode = {
def fromRationalTiles(dir: RationalDirection, adapt: () => TLNodeChain, name: Option[String] = None): TLRationalInwardNode = {
val adapters = adapt() // wanted to be called inside SystemBus scope
val tile_sink = LazyModule(new TLRationalCrossingSink(direction = dir))
name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
adapters.in :=* tile_sink.node
master_splitter.node :=* adapters.out
tile_sink.node
}
def fromAsyncTiles(depth: Int, sync: Int, adapt: () => TLNodeChain, name: Option[String] = None): TLAsyncInwardNode = {
val adapters = adapt() // wanted to be called inside SystemBus scope
val tile_sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
val (in, out) = bufferChain(port.addBuffers, name = name)
tile_fixer.node :=* out
in :=* tile_sink.node
adapters.in :=* tile_sink.node
master_splitter.node :=* adapters.out
tile_sink.node
}