diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 90dcbd36..cbb2df0f 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -459,7 +459,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
   .otherwise {
     ex_reg_br_type     := id_br_type;
     ex_reg_jalr        := id_jalr
-    ex_reg_btb_hit     := io.imem.resp.bits.taken
+    ex_reg_btb_hit     := io.imem.resp.bits.taken && !id_jalr
     ex_reg_div_mul_val := id_mul_val || id_div_val
     ex_reg_mem_val     := id_mem_val.toBool;
     ex_reg_valid       := Bool(true)
@@ -484,9 +484,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
   val replay_ex_other = wb_dcache_miss && ex_reg_load_use || mem_reg_replay_next
   val replay_ex = replay_ex_structural || replay_ex_other
   ctrl_killx := take_pc_wb || replay_ex
-  val take_pc_ex = Mux(ex_reg_jalr,
-    !(ex_reg_btb_hit && io.dpath.jalr_eq) && !replay_ex_other,
-    ex_reg_btb_hit != io.dpath.ex_br_taken)
+  val take_pc_ex = ex_reg_jalr && !io.dpath.jalr_eq || io.dpath.ex_br_taken
   // detect 2-cycle load-use delay for LB/LH/SC
   val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || AVec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type)
 
@@ -714,7 +712,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
   io.dpath.pcr      := wb_reg_pcr.toUInt
   io.dpath.eret := wb_reg_eret
   io.dpath.ex_mem_type := ex_reg_mem_type
-  io.dpath.ex_br_type := ex_reg_br_type
+  io.dpath.ex_br_type := ex_reg_br_type ^ ex_reg_btb_hit
   io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val
   io.dpath.ex_rocc_val := ex_reg_rocc_val
   io.dpath.mem_rocc_val := mem_reg_rocc_val
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 0f5255fc..ed1a5e9d 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -185,7 +185,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
     e(0)))
   }
   val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs1, ex_reg_pc)
-  val ex_br_offset = Mux(io.ctrl.ex_predicted_taken && !io.ctrl.ex_jalr, SInt(4), ex_imm(19,0).toSInt)
+  val ex_br_offset = Mux(io.ctrl.ex_predicted_taken, SInt(4), ex_imm(19,0).toSInt)
   val ex_br64 = ex_br_base + ex_br_offset
   val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs1, ex_br64), vaSign(ex_reg_pc, ex_br64))
   val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0))
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 180caf32..8a60548b 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -160,11 +160,11 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
   val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits)
 
   val s0_valid = io.req.valid || s1_valid && stall
-  val s0_pgoff = Mux(io.req.valid, io.req.bits.idx, s1_pgoff)
+  val s0_pgoff = Mux(s1_valid && stall, s1_pgoff, io.req.bits.idx)
 
   s1_valid := io.req.valid && rdy || s1_valid && stall && !io.req.bits.kill
   when (io.req.valid && rdy) {
-    s1_pgoff := s0_pgoff
+    s1_pgoff := io.req.bits.idx
   }
 
   s2_valid := s1_valid && rdy && !io.req.bits.kill || io.resp.valid && stall