riscv/rocket-chip
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Pipeline FMAs more deeply by default

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Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
This commit is contained in:
Andrew Waterman 2016-09-08 21:27:28 -07:00
parent eaa4b04ee5
commit 656aa78f7d
1 changed files with 2 additions and 2 deletions
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src/main/scala/rocket/fpu.scala
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@ -12,8 +12,8 @@ import cde.{Parameters, Field}
case class FPUConfig( case class FPUConfig(
divSqrt: Boolean = true, divSqrt: Boolean = true,
sfmaLatency: Int = 2, sfmaLatency: Int = 3,
dfmaLatency: Int = 3 dfmaLatency: Int = 4
) )
object FPConstants object FPConstants