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SystemBus: split FIFOFixers along bus boundaries

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If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
This commit is contained in:
Wesley W. Terpstra 2017-08-30 13:28:11 -07:00
parent bf19440db5
commit 656609d610
1 changed files with 3 additions and 1 deletions
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4
src/main/scala/coreplex/SystemBus.scala
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@ -29,12 +29,14 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
master_splitter.node :=* tile_fixer.node
master_splitter.node :=* port_fixer.node
pbus_fixer.node :*= outwardWWNode
def toSplitSlaves: TLOutwardNode = outwardSplitNode
val toPeripheryBus: TLOutwardNode = outwardWWNode
val toPeripheryBus: TLOutwardNode = pbus_fixer.node
val toMemoryBus: TLOutwardNode = outwardNode