SystemBus: split FIFOFixers along bus boundaries
If you have a system with a lot of periphery slaves, you wan to FIFO fix them on the periphery bus rather than paying the circuit cost at the sbus.
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@ -29,12 +29,14 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
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private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
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private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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master_splitter.node :=* tile_fixer.node
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master_splitter.node :=* tile_fixer.node
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master_splitter.node :=* port_fixer.node
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master_splitter.node :=* port_fixer.node
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pbus_fixer.node :*= outwardWWNode
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def toSplitSlaves: TLOutwardNode = outwardSplitNode
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def toSplitSlaves: TLOutwardNode = outwardSplitNode
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val toPeripheryBus: TLOutwardNode = outwardWWNode
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val toPeripheryBus: TLOutwardNode = pbus_fixer.node
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val toMemoryBus: TLOutwardNode = outwardNode
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val toMemoryBus: TLOutwardNode = outwardNode
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