riscv/rocket-chip
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tilelink: increase Fuzzer source reuse aggression

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This commit is contained in:
Wesley W. Terpstra 2017-07-26 11:57:24 -07:00
parent 1efdca106c
commit 6550ae2e31
1 changed files with 12 additions and 16 deletions
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28
src/main/scala/tilelink/Fuzzer.scala
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@ -14,12 +14,11 @@ class IDMapGenerator(numIds: Int) extends Module {
val alloc = Decoupled(UInt(width = w)) val alloc = Decoupled(UInt(width = w))
} }
io.free.ready := Bool(true)
// True indicates that the id is available // True indicates that the id is available
val bitmap = RegInit(UInt((BigInt(1) << numIds) - 1, width = numIds)) val bitmap = RegInit(UInt((BigInt(1) << numIds) - 1, width = numIds))
io.free.ready := Bool(true)
assert (!io.free.valid || !bitmap(io.free.bits)) // No double freeing
val select = ~(leftOR(bitmap) << 1) & bitmap val select = ~(leftOR(bitmap) << 1) & bitmap
io.alloc.bits := OHToUInt(select) io.alloc.bits := OHToUInt(select)
io.alloc.valid := bitmap.orR() io.alloc.valid := bitmap.orR()
@ -31,6 +30,7 @@ class IDMapGenerator(numIds: Int) extends Module {
when (io.free.fire()) { set := UIntToOH(io.free.bits) } when (io.free.fire()) { set := UIntToOH(io.free.bits) }
bitmap := (bitmap & ~clr) | set bitmap := (bitmap & ~clr) | set
assert (!io.free.valid || !(bitmap & ~clr)(io.free.bits)) // No double freeing
} }
object LFSR64 object LFSR64
@ -111,7 +111,7 @@ class TLFuzzer(
val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations+1))) val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations+1)))
val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations+1))) val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations+1)))
if (nOperations>0) { if (nOperations>0) {
io.finished := num_resps === UInt(0) io.finished := num_resps === UInt(0)
} else { } else {
io.finished := Bool(false) io.finished := Bool(false)
} }
@ -125,12 +125,7 @@ class TLFuzzer(
// Source ID generation // Source ID generation
val idMap = Module(new IDMapGenerator(inFlight)) val idMap = Module(new IDMapGenerator(inFlight))
val alloc = Queue.irrevocable(idMap.io.alloc, 1, pipe = true) val src = idMap.io.alloc.bits holdUnless a_first
val src = alloc.bits
alloc.ready := req_done
idMap.io.free.valid := resp_done
idMap.io.free.bits := out.d.bits.source
// Increment random number generation for the following subfields // Increment random number generation for the following subfields
val inc = Wire(Bool()) val inc = Wire(Bool())
val inc_beat = Wire(Bool()) val inc_beat = Wire(Bool())
@ -183,12 +178,13 @@ class TLFuzzer(
UInt("b100") -> lbits, UInt("b100") -> lbits,
UInt("b101") -> hbits)) UInt("b101") -> hbits))
// Wire both the used and un-used channel signals // Wire up Fuzzer flow control
if (nOperations>0) { val a_gen = if (nOperations>0) num_reqs =/= UInt(0) else Bool(true)
out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0) out.a.valid := a_gen && legal && (!a_first || idMap.io.alloc.valid)
} else { idMap.io.alloc.ready := a_gen && legal && a_first && out.a.ready
out.a.valid := legal && alloc.valid idMap.io.free.valid := d_first && out.d.fire()
} idMap.io.free.bits := out.d.bits.source
out.a.bits := bits out.a.bits := bits
out.b.ready := Bool(true) out.b.ready := Bool(true)
out.c.valid := Bool(false) out.c.valid := Bool(false)