riscv/rocket-chip
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Merge pull request #1018 from freechipsproject/refine-trace-port

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Separate interrupt bit from cause field in trace bundle
This commit is contained in:
Henry Cook 2017-09-27 14:46:27 -07:00 committed by GitHub
commit 652d57291c
1 changed files with 5 additions and 3 deletions
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8
src/main/scala/rocket/CSR.scala
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@ -155,7 +155,8 @@ class TracedInstruction(implicit p: Parameters) extends CoreBundle {
val insn = UInt(width = iLen)
val priv = UInt(width = 3)
val exception = Bool()
val cause = UInt(width = 1 + log2Ceil(xLen))
val interrupt = Bool()
val cause = UInt(width = log2Ceil(xLen))
val tval = UInt(width = coreMaxAddrBits max iLen)
}
@ -519,7 +520,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
assert(!reg_singleStepped || io.retire === UInt(0))
val epc = ~(~io.pc | (coreInstBytes-1))
val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint,
val write_badaddr = exception && cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store,
Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
@ -773,7 +774,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
t.insn := insn
t.iaddr := io.pc
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := Cat(cause(xLen-1), cause(log2Ceil(xLen)-1, 0))
t.cause := cause
t.interrupt := cause(xLen-1)
t.tval := badaddr_value
}