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axi4: add a minLatency parameter

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This commit is contained in:
Wesley W. Terpstra
2017-01-23 17:54:27 -08:00
parent 46cdfc2b45
commit 64e1de751d
10 changed files with 32 additions and 26 deletions
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4
src/main/scala/uncore/tilelink2/Buffer.scala
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@ -18,8 +18,8 @@ class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe:
require (e >= 0)
val node = TLAdapterNode(
clientFn = { seq => seq(0).copy(minLatency = seq(0).minLatency + min(1,b) + min(1,c)) },
managerFn = { seq => seq(0).copy(minLatency = seq(0).minLatency + min(1,a) + min(1,d)) })
clientFn = { case Seq(p) => p.copy(minLatency = p.minLatency + min(1,b) + min(1,c)) },
managerFn = { case Seq(p) => p.copy(minLatency = p.minLatency + min(1,a) + min(1,d)) })
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {

4
src/main/scala/uncore/tilelink2/Crossing.scala
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@ -10,7 +10,7 @@ import util._
class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = TLAsyncSourceNode()
val node = TLAsyncSourceNode(sync)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
@ -44,7 +44,7 @@ class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyM
class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = TLAsyncSinkNode(depth)
val node = TLAsyncSinkNode(depth, sync)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {

12
src/main/scala/uncore/tilelink2/Nodes.scala
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@ -169,14 +169,14 @@ case class TLAsyncIdentityNode() extends IdentityNode(TLAsyncImp)
case class TLAsyncOutputNode() extends OutputNode(TLAsyncImp)
case class TLAsyncInputNode() extends InputNode(TLAsyncImp)
case class TLAsyncSourceNode() extends MixedNode(TLImp, TLAsyncImp)(
dFn = { case (1, s) => s.map(TLAsyncClientPortParameters(_)) },
uFn = { case (1, s) => s.map(_.base) },
case class TLAsyncSourceNode(sync: Int) extends MixedNode(TLImp, TLAsyncImp)(
dFn = { case (1, Seq(p)) => Seq(TLAsyncClientPortParameters(p)) },
uFn = { case (1, Seq(p)) => Seq(p.base.copy(minLatency = sync+1)) }, // discard cycles in other clock domain
numPO = 1 to 1,
numPI = 1 to 1)
case class TLAsyncSinkNode(depth: Int) extends MixedNode(TLAsyncImp, TLImp)(
dFn = { case (1, s) => s.map(_.base) },
uFn = { case (1, s) => s.map(TLAsyncManagerPortParameters(depth, _)) },
case class TLAsyncSinkNode(depth: Int, sync: Int) extends MixedNode(TLAsyncImp, TLImp)(
dFn = { case (1, Seq(p)) => Seq(p.base.copy(minLatency = sync+1)) },
uFn = { case (1, Seq(p)) => Seq(TLAsyncManagerPortParameters(depth, p)) },
numPO = 1 to 1,
numPI = 1 to 1)

2
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -18,7 +18,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int =
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1))) // the Queue adds at least one cycle
minLatency = min(concurrency, 1))) // the Queue adds at most one cycle
{
require (address.contiguous)

10
src/main/scala/uncore/tilelink2/ToAXI4.scala
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@ -19,8 +19,8 @@ case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
aligned = true))
Seq(AXI4MasterPortParameters(masters))
},
uFn = { case (1, Seq(AXI4SlavePortParameters(slaves, beatBytes))) =>
val managers = slaves.map { case s =>
uFn = { case (1, Seq(p)) => Seq(TLManagerPortParameters(
managers = p.slaves.map { case s =>
TLManagerParameters(
address = s.address,
regionType = s.regionType,
@ -28,10 +28,10 @@ case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
nodePath = s.nodePath,
supportsGet = s.supportsRead,
supportsPutFull = s.supportsWrite,
supportsPutPartial = s.supportsWrite)
supportsPutPartial = s.supportsWrite)},
// AXI4 is NEVER fifo in TL sense (R+W are independent)
}
Seq(TLManagerPortParameters(managers, beatBytes, 1, 0))
beatBytes = p.beatBytes,
minLatency = p.minLatency))
},
numPO = 1 to 1,
numPI = 1 to 1)