axi4: add a minLatency parameter

src/main/scala/uncore/axi4/Buffer.scala

@@ -6,7 +6,7 @@ import Chisel._
 import chisel3.internal.sourceinfo.SourceInfo
 import config._
 import diplomacy._
-import scala.math.max
+import scala.math.{min,max}
 
 // pipe is only used if a queue has depth = 1
 class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule
@@ -17,7 +17,9 @@ class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, p
   require (ar >= 0)
   require (r  >= 0)
 
-  val node = AXI4IdentityNode()
+  val node = AXI4AdapterNode(
+    masterFn = { case Seq(p) => p },
+    slaveFn  = { case Seq(p) => p.copy(minLatency = p.minLatency + min(1,min(aw,ar)) + min(1,min(r,b))) })
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {

src/main/scala/uncore/axi4/Parameters.scala

@@ -29,8 +29,9 @@ case class AXI4SlaveParameters(
 }
 
 case class AXI4SlavePortParameters(
-  slaves:    Seq[AXI4SlaveParameters],
-  beatBytes: Int)
+  slaves:     Seq[AXI4SlaveParameters],
+  beatBytes:  Int,
+  minLatency: Int = 1)
 {
   require (!slaves.isEmpty)
   require (isPow2(beatBytes))

src/main/scala/uncore/axi4/RegisterRouter.scala

@@ -16,7 +16,8 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
       supportsWrite = TransferSizes(1, beatBytes),
       supportsRead  = TransferSizes(1, beatBytes),
       interleavedId = Some(0))),
-    beatBytes  = beatBytes))
+    beatBytes  = beatBytes,
+    minLatency = min(concurrency, 1))) // the Queue adds at most one cycle
 {
   require (address.contiguous)
 

src/main/scala/uncore/axi4/SRAM.scala

@@ -16,7 +16,8 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
       supportsRead  = TransferSizes(1, beatBytes),
       supportsWrite = TransferSizes(1, beatBytes),
       interleavedId = Some(0))),
-    beatBytes  = beatBytes))
+    beatBytes  = beatBytes,
+    minLatency = 0)) // B responds on same cycle
 
   // We require the address range to include an entire beat (for the write mask)
   require ((address.mask & (beatBytes-1)) == beatBytes-1)

src/main/scala/uncore/axi4/ToTL.scala

@@ -16,8 +16,8 @@ case class AXI4ToTLNode() extends MixedNode(AXI4Imp, TLImp)(
         nodePath = m.nodePath)
     }))
   },
-  uFn = { case (1, Seq(TLManagerPortParameters(managers, beatBytes, _, _))) =>
-    Seq(AXI4SlavePortParameters(beatBytes = beatBytes, slaves = managers.map { m =>
+  uFn = { case (1, Seq(mp)) => Seq(AXI4SlavePortParameters(
+    slaves = mp.managers.map { m =>
       AXI4SlaveParameters(
         address       = m.address,
         regionType    = m.regionType,
@@ -25,8 +25,9 @@ case class AXI4ToTLNode() extends MixedNode(AXI4Imp, TLImp)(
         nodePath      = m.nodePath,
         supportsWrite = m.supportsPutPartial,
         supportsRead  = m.supportsGet,
-        interleavedId = Some(0)) // TL2 never interleaves D beats
-    }))
+        interleavedId = Some(0))}, // TL2 never interleaves D beats
+    beatBytes = mp.beatBytes,
+    minLatency = mp.minLatency))
   },
   numPO = 1 to 1,
   numPI = 1 to 1)