riscv/rocket-chip
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make sure voluntary releases don't get allocated to L2WritebackUnit

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This commit is contained in:
Howard Mao 2016-07-06 14:10:45 -07:00
parent b105076996
commit 64afc795fd
4 changed files with 16 additions and 16 deletions
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6
uncore/src/main/scala/agents/Broadcast.scala
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@ -108,8 +108,7 @@ class BufferedBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Param
with HasDataBuffer { with HasDataBuffer {
// Tell the parent if any incoming messages conflict with the ongoing transaction // Tell the parent if any incoming messages conflict with the ongoing transaction
routeInParent() routeInParent(irelCanAlloc = Bool(true))
io.alloc.iacq.can := Bool(false)
// Start transaction by accepting inner release // Start transaction by accepting inner release
innerRelease(block_vol_ignt = pending_orel || vol_ognt_counter.pending) innerRelease(block_vol_ignt = pending_orel || vol_ognt_counter.pending)
@ -133,8 +132,7 @@ class BufferedBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
with HasByteWriteMaskBuffer { with HasByteWriteMaskBuffer {
// Setup IOs used for routing in the parent // Setup IOs used for routing in the parent
routeInParent() routeInParent(iacqCanAlloc = Bool(true))
io.alloc.irel.can := Bool(false)
// First, take care of accpeting new acquires or secondary misses // First, take care of accpeting new acquires or secondary misses
// Handling of primary and secondary misses' data and write mask merging // Handling of primary and secondary misses' data and write mask merging

6
uncore/src/main/scala/agents/Bufferless.scala
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@ -72,8 +72,7 @@ class BufferlessBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Par
extends BroadcastVoluntaryReleaseTracker(trackerId)(p) { extends BroadcastVoluntaryReleaseTracker(trackerId)(p) {
// Tell the parent if any incoming messages conflict with the ongoing transaction // Tell the parent if any incoming messages conflict with the ongoing transaction
routeInParent() routeInParent(irelCanAlloc = Bool(true))
io.alloc.iacq.can := Bool(false)
// Start transaction by accepting inner release // Start transaction by accepting inner release
innerRelease(block_vol_ignt = pending_orel || vol_ognt_counter.pending) innerRelease(block_vol_ignt = pending_orel || vol_ognt_counter.pending)
@ -94,8 +93,7 @@ class BufferlessBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
extends BroadcastAcquireTracker(trackerId)(p) { extends BroadcastAcquireTracker(trackerId)(p) {
// Setup IOs used for routing in the parent // Setup IOs used for routing in the parent
routeInParent() routeInParent(iacqCanAlloc = Bool(true))
io.alloc.irel.can := Bool(false)
// First, take care of accpeting new acquires or secondary misses // First, take care of accpeting new acquires or secondary misses
// Handling of primary and secondary misses' data and write mask merging // Handling of primary and secondary misses' data and write mask merging

9
uncore/src/main/scala/agents/Cache.scala
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@ -729,8 +729,9 @@ class CacheVoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters)
pinAllReadyValidLow(io) pinAllReadyValidLow(io)
// Avoid metatdata races with writebacks // Avoid metatdata races with writebacks
routeInParent(iacqMatches = inSameSet(_, xact_addr_block)) routeInParent(
io.alloc.iacq.can := Bool(false) iacqMatches = inSameSet(_, xact_addr_block),
irelCanAlloc = Bool(true))
// Initialize and accept pending Release beats // Initialize and accept pending Release beats
innerRelease( innerRelease(
@ -811,8 +812,8 @@ class CacheAcquireTracker(trackerId: Int)(implicit p: Parameters)
routeInParent( routeInParent(
iacqMatches = inSameSet(_, xact_addr_block), iacqMatches = inSameSet(_, xact_addr_block),
irelMatches = (irel: HasCacheBlockAddress) => irelMatches = (irel: HasCacheBlockAddress) =>
Mux(before_wb_alloc, inSameSet(irel, xact_addr_block), exactAddrMatch(irel))) Mux(before_wb_alloc, inSameSet(irel, xact_addr_block), exactAddrMatch(irel)),
io.alloc.irel.can := Bool(false) iacqCanAlloc = Bool(true))
// TileLink allows for Gets-under-Get // TileLink allows for Gets-under-Get
// and Puts-under-Put, and either may also merge with a preceding prefetch // and Puts-under-Put, and either may also merge with a preceding prefetch

11
uncore/src/main/scala/agents/Trackers.scala
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@ -380,13 +380,16 @@ trait RoutesInParent extends HasBlockAddressBuffer
def exactAddrMatch(a: HasCacheBlockAddress): Bool = a.conflicts(xact_addr_block) def exactAddrMatch(a: HasCacheBlockAddress): Bool = a.conflicts(xact_addr_block)
def routeInParent(iacqMatches: AddrComparison = exactAddrMatch, def routeInParent(iacqMatches: AddrComparison = exactAddrMatch,
irelMatches: AddrComparison = exactAddrMatch, irelMatches: AddrComparison = exactAddrMatch,
oprbMatches: AddrComparison = exactAddrMatch) { oprbMatches: AddrComparison = exactAddrMatch,
iacqCanAlloc: Bool = Bool(false),
irelCanAlloc: Bool = Bool(false),
oprbCanAlloc: Bool = Bool(false)) {
io.alloc.iacq.matches := (state =/= s_idle) && iacqMatches(io.iacq()) io.alloc.iacq.matches := (state =/= s_idle) && iacqMatches(io.iacq())
io.alloc.irel.matches := (state =/= s_idle) && irelMatches(io.irel()) io.alloc.irel.matches := (state =/= s_idle) && irelMatches(io.irel())
io.alloc.oprb.matches := (state =/= s_idle) && oprbMatches(io.oprb()) io.alloc.oprb.matches := (state =/= s_idle) && oprbMatches(io.oprb())
io.alloc.iacq.can := state === s_idle io.alloc.iacq.can := state === s_idle && iacqCanAlloc
io.alloc.irel.can := state === s_idle io.alloc.irel.can := state === s_idle && irelCanAlloc
io.alloc.oprb.can := Bool(false) io.alloc.oprb.can := state === s_idle && oprbCanAlloc
} }
} }