split coreplex off into separate package

coreplex/build.sbt

@@ -0,0 +1,10 @@
+organization := "edu.berkeley.cs"
+
+version := "1.0"
+
+name := "coreplex"
+
+scalaVersion := "2.11.6"
+
+libraryDependencies ++= (Seq("chisel", "uncore", "junctions", "rocket", "groundtest").map {
+  dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten

coreplex/src/main/scala/Configs.scala

@@ -0,0 +1,408 @@
+// See LICENSE for license details.
+
+package coreplex
+
+import Chisel._
+import junctions._
+import uncore.tilelink._
+import uncore.coherence._
+import uncore.agents._
+import uncore.devices._
+import uncore.converters._
+import rocket._
+import rocket.Util._
+import scala.math.max
+import scala.collection.mutable.{LinkedHashSet, ListBuffer}
+import DefaultTestSuites._
+import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+
+object ConfigUtils {
+  def max_int(values: Int*): Int = {
+    values.reduce((a, b) => max(a, b))
+  }
+}
+import ConfigUtils._
+
+class BaseCoreplexConfig extends Config (
+  topDefinitions = { (pname,site,here) => 
+    type PF = PartialFunction[Any,Any]
+    def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
+    lazy val innerDataBits = 64
+    lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
+    pname match {
+      //Memory Parameters
+      case PAddrBits => 32
+      case PgIdxBits => 12
+      case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
+      case PgLevelBits => site(PgIdxBits) - log2Up(site(XLen)/8)
+      case VPNBits => site(PgLevels) * site(PgLevelBits)
+      case PPNBits => site(PAddrBits) - site(PgIdxBits)
+      case VAddrBits => site(VPNBits) + site(PgIdxBits)
+      case ASIdBits => 7
+      //Params used by all caches
+      case NSets => findBy(CacheName)
+      case NWays => findBy(CacheName)
+      case RowBits => findBy(CacheName)
+      case NTLBEntries => findBy(CacheName)
+      case CacheIdBits => findBy(CacheName)
+      case SplitMetadata => findBy(CacheName)
+      case "L1I" => {
+        case NSets => Knob("L1I_SETS") //64
+        case NWays => Knob("L1I_WAYS") //4
+        case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
+        case NTLBEntries => 8
+        case CacheIdBits => 0
+        case SplitMetadata => false
+      }:PF
+      case "L1D" => {
+        case NSets => Knob("L1D_SETS") //64
+        case NWays => Knob("L1D_WAYS") //4
+        case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
+        case NTLBEntries => 8
+        case CacheIdBits => 0
+        case SplitMetadata => false
+      }:PF
+      case ECCCode => None
+      case Replacer => () => new RandomReplacement(site(NWays))
+      case AmoAluOperandBits => site(XLen)
+      //L1InstCache
+      case BtbKey => BtbParameters()
+      //L1DataCache
+      case WordBits => site(XLen)
+      case StoreDataQueueDepth => 17
+      case ReplayQueueDepth => 16
+      case NMSHRs => Knob("L1D_MSHRS")
+      case LRSCCycles => 32 
+      //L2 Memory System Params
+      case NAcquireTransactors => 7
+      case L2StoreDataQueueDepth => 1
+      case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
+      case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
+        Module(new L2BroadcastHub()(p.alterPartial({
+          case InnerTLId => "L1toL2"
+          case OuterTLId => "L2toMC" })))
+      case NCachedTileLinkPorts => 1
+      case NUncachedTileLinkPorts => 1
+      //Tile Constants
+      case BuildTiles => {
+        val (rvi, rvu) =
+          if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
+          else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
+        TestGeneration.addSuites(rvi.map(_("p")))
+        TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
+        TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)
+        List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
+          Module(new RocketTile(resetSignal = r)(p.alterPartial({
+            case TLId => "L1toL2"
+            case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)
+          })))
+        }
+      }
+      case BuildRoCC => Nil
+      case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
+      case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
+      case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
+      //Rocket Core Constants
+      case FetchWidth => if (site(UseCompressed)) 2 else 1
+      case RetireWidth => 1
+      case UseVM => true
+      case UseUser => true
+      case UseDebug => true
+      case NBreakpoints => 1
+      case UsePerfCounters => true
+      case FastLoadWord => true
+      case FastLoadByte => false
+      case MulUnroll => 8
+      case DivEarlyOut => true
+      case XLen => 64
+      case UseFPU => {
+        val env = if(site(UseVM)) List("p","v") else List("p")
+        TestGeneration.addSuite(rv32udBenchmarks)
+        if(site(FDivSqrt)) {
+          TestGeneration.addSuites(env.map(rv64uf))
+          TestGeneration.addSuites(env.map(rv64ud))
+        } else {
+          TestGeneration.addSuites(env.map(rv64ufNoDiv))
+          TestGeneration.addSuites(env.map(rv64udNoDiv))
+        }
+        true
+      }
+      case UseAtomics => {
+        val env = if(site(UseVM)) List("p","v") else List("p")
+        TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
+        true
+      }
+      case UseCompressed => {
+        val env = if(site(UseVM)) List("p","v") else List("p")
+        TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc))
+        true
+      }
+      case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
+      case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
+      case FDivSqrt => true
+      case SFMALatency => 2
+      case DFMALatency => 3
+      case CoreInstBits => if (site(UseCompressed)) 16 else 32
+      case CoreDataBits => site(XLen)
+      case NCustomMRWCSRs => 0
+      case ResetVector => BigInt(0x1000)
+      case MtvecInit => BigInt(0x1010)
+      case MtvecWritable => true
+      //Uncore Paramters
+      case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
+      case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
+      case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
+                             log2Up(site(TLKey(site(TLId))).nClients)
+      case TLKey("L1toL2") => {
+        val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
+        TileLinkParameters(
+          coherencePolicy = (
+            if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
+            else new MESICoherence(site(L2DirectoryRepresentation))),
+          nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
+          nCachingClients = site(NCachedTileLinkPorts),
+          nCachelessClients = (if (site(ExportBusPort)) 1 else 0) + site(NUncachedTileLinkPorts),
+          maxClientXacts = max_int(
+              // L1 cache
+              site(NMSHRs) + 1 /* IOMSHR */,
+              // RoCC
+              if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
+          maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
+          maxManagerXacts = site(NAcquireTransactors) + 2,
+          dataBeats = innerDataBeats,
+          dataBits = site(CacheBlockBytes)*8)
+      }
+      case TLKey("L2toMC") => 
+        TileLinkParameters(
+          coherencePolicy = new MEICoherence(
+            new NullRepresentation(site(NBanksPerMemoryChannel))),
+          nManagers = 1,
+          nCachingClients = site(NBanksPerMemoryChannel),
+          nCachelessClients = 0,
+          maxClientXacts = 1,
+          maxClientsPerPort = site(NAcquireTransactors) + 2,
+          maxManagerXacts = 1,
+          dataBeats = innerDataBeats,
+          dataBits = site(CacheBlockBytes)*8)
+      case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
+        maxClientXacts = site(NAcquireTransactors) + 2,
+        maxClientsPerPort = site(NBanksPerMemoryChannel),
+        dataBeats = site(MIFDataBeats))
+      case TLKey("L2toMMIO") => {
+        TileLinkParameters(
+          coherencePolicy = new MICoherence(
+            new NullRepresentation(site(NBanksPerMemoryChannel))),
+          nManagers = site(GlobalAddrMap).subMap("io").numSlaves,
+          nCachingClients = 0,
+          nCachelessClients = 1,
+          maxClientXacts = 4,
+          maxClientsPerPort = 1,
+          maxManagerXacts = 1,
+          dataBeats = innerDataBeats,
+          dataBits = site(CacheBlockBytes) * 8)
+      }
+      case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
+
+      case BootROMFile => "./bootrom/bootrom.img"
+      case NTiles => Knob("NTILES")
+      case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
+      case BankIdLSB => 0
+      case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
+      case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
+      case EnableL2Logging => false
+      case ExtraCoreplexPorts => (p: Parameters) => new Bundle
+      case RegressionTestNames => LinkedHashSet(
+        "rv64ud-v-fcvt",
+        "rv64ud-p-fdiv",
+        "rv64ud-v-fadd",
+        "rv64uf-v-fadd",
+        "rv64um-v-mul",
+        "rv64mi-p-breakpoint",
+        "rv64uc-v-rvc",
+        "rv64ud-v-structural",
+        "rv64si-p-wfi",
+        "rv64um-v-divw",
+        "rv64ua-v-lrsc",
+        "rv64ui-v-fence_i",
+        "rv64ud-v-fcvt_w",
+        "rv64uf-v-fmin",
+        "rv64ui-v-sb",
+        "rv64ua-v-amomax_d",
+        "rv64ud-v-move",
+        "rv64ud-v-fclass",
+        "rv64ua-v-amoand_d",
+        "rv64ua-v-amoxor_d",
+        "rv64si-p-sbreak",
+        "rv64ud-v-fmadd",
+        "rv64uf-v-ldst",
+        "rv64um-v-mulh",
+        "rv64si-p-dirty")
+      case _ => throw new CDEMatchError
+  }},
+  knobValues = {
+    case "NTILES" => 1
+    case "NBANKS_PER_MEM_CHANNEL" => 1
+    case "L1D_MSHRS" => 2
+    case "L1D_SETS" => 64
+    case "L1D_WAYS" => 4
+    case "L1I_SETS" => 64
+    case "L1I_WAYS" => 4
+    case _ => throw new CDEMatchError
+  }
+)
+
+class WithNCores(n: Int) extends Config(
+  knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
+
+class WithNBanksPerMemChannel(n: Int) extends Config(
+  knobValues = {
+    case "NBANKS_PER_MEM_CHANNEL" => n
+    case _ => throw new CDEMatchError
+  })
+
+class WithL2Cache extends Config(
+  (pname,site,here) => pname match {
+    case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
+    case "L2Bank" => {
+      case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
+                        site(CacheBlockBytes)) /
+                          (site(NBanksPerMemoryChannel)*site(NMemoryChannels))) /
+                            site(NWays)
+      case NWays => Knob("L2_WAYS")
+      case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
+      case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
+      case SplitMetadata => Knob("L2_SPLIT_METADATA")
+    }: PartialFunction[Any,Any] 
+    case NAcquireTransactors => 2
+    case NSecondaryMisses => 4
+    case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
+    case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
+      Module(new L2HellaCacheBank()(p.alterPartial({
+        case CacheId => id
+        case CacheName => "L2Bank"
+        case InnerTLId => "L1toL2"
+        case OuterTLId => "L2toMC"})))
+    case L2Replacer => () => new SeqRandom(site(NWays))
+    case _ => throw new CDEMatchError
+  },
+  knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError }
+)
+
+class WithBufferlessBroadcastHub extends Config(
+  (pname, site, here) => pname match {
+    case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
+      Module(new BufferlessBroadcastHub()(p.alterPartial({
+        case InnerTLId => "L1toL2"
+        case OuterTLId => "L2toMC" })))
+  })
+
+/**
+ * WARNING!!! IGNORE AT YOUR OWN PERIL!!!
+ *
+ * There is a very restrictive set of conditions under which the stateless
+ * bridge will function properly. There can only be a single tile. This tile
+ * MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
+ * uncached channel capable of writes (i.e. a RoCC accelerator).
+ *
+ * This is because the stateless bridge CANNOT generate probes, so if your
+ * system depends on coherence between channels in any way,
+ * DO NOT use this configuration.
+ */
+class WithStatelessBridge extends Config (
+  topDefinitions = (pname, site, here) => pname match {
+    case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
+      Module(new ManagerToClientStatelessBridge()(p.alterPartial({
+        case InnerTLId => "L1toL2"
+        case OuterTLId => "L2toMC" })))
+  },
+  knobValues = {
+    case "L1D_MSHRS" => 0
+    case _ => throw new CDEMatchError
+  }
+)
+
+class WithPLRU extends Config(
+  (pname, site, here) => pname match {
+    case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
+    case _ => throw new CDEMatchError
+  })
+
+class WithL2Capacity(size_kb: Int) extends Config(
+  knobValues = {
+    case "L2_CAPACITY_IN_KB" => size_kb
+    case _ => throw new CDEMatchError
+  })
+
+class WithNL2Ways(n: Int) extends Config(
+  knobValues = {
+    case "L2_WAYS" => n
+    case _ => throw new CDEMatchError
+  })
+
+class WithRV32 extends Config(
+  (pname,site,here) => pname match {
+    case XLen => 32
+    case UseVM => false
+    case UseUser => false
+    case UseAtomics => false
+    case UseFPU => false
+    case RegressionTestNames => LinkedHashSet(
+      "rv32mi-p-ma_addr",
+      "rv32mi-p-csr",
+      "rv32ui-p-sh",
+      "rv32ui-p-lh",
+      "rv32mi-p-sbreak",
+      "rv32ui-p-sll")
+    case _ => throw new CDEMatchError
+  }
+)
+
+class WithBlockingL1 extends Config (
+  knobValues = {
+    case "L1D_MSHRS" => 0
+    case _ => throw new CDEMatchError
+  }
+)
+
+class WithSmallCores extends Config (
+    topDefinitions = { (pname,site,here) => pname match {
+      case UseFPU => false
+      case MulUnroll => 1
+      case DivEarlyOut => false  
+      case NTLBEntries => 4
+      case BtbKey => BtbParameters(nEntries = 0)
+      case StoreDataQueueDepth => 2
+      case ReplayQueueDepth => 2
+      case NAcquireTransactors => 2
+      case _ => throw new CDEMatchError
+    }},
+  knobValues = {
+    case "L1D_SETS" => 64
+    case "L1D_WAYS" => 1
+    case "L1I_SETS" => 64
+    case "L1I_WAYS" => 1
+    case "L1D_MSHRS" => 0
+    case _ => throw new CDEMatchError
+  }
+)
+
+class WithRoccExample extends Config(
+  (pname, site, here) => pname match {
+    case BuildRoCC => Seq(
+      RoccParameters(
+        opcodes = OpcodeSet.custom0,
+        generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
+      RoccParameters(
+        opcodes = OpcodeSet.custom1,
+        generator = (p: Parameters) => Module(new TranslatorExample()(p)),
+        nPTWPorts = 1),
+      RoccParameters(
+        opcodes = OpcodeSet.custom2,
+        generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
+
+    case RoccMaxTaggedMemXacts => 1
+    case _ => throw new CDEMatchError
+  })
+
+class WithSplitL2Metadata extends Config(
+  knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })

coreplex/src/main/scala/Coreplex.scala

@@ -1,4 +1,4 @@
-package rocketchip
+package coreplex
 
 import Chisel._
 import cde.{Parameters, Field}
@@ -38,8 +38,8 @@ case object BootROMFile extends Field[String]
 case object ExportMMIOPort extends Field[Boolean]
 /** Expose an additional bus master port */
 case object ExportBusPort extends Field[Boolean]
-/** Function for building Coreplex */
+/** Extra top-level ports exported from the coreplex */
-case object BuildCoreplex extends Field[Parameters => Coreplex]
+case object ExtraCoreplexPorts extends Field[Parameters => Bundle]
 
 trait HasCoreplexParameters {
   implicit val p: Parameters
@@ -234,6 +234,7 @@ class CoreplexIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
   val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None
   val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
   val debug = new DebugBusIO()(p).flip
+  val extra = p(ExtraCoreplexPorts)(p)
 }
 
 abstract class Coreplex(implicit val p: Parameters) extends Module

coreplex/src/main/scala/DirectGroundTest.scala

@@ -1,4 +1,4 @@
-package rocketchip
+package coreplex
 
 import Chisel._
 import cde.{Parameters, Field}
@@ -9,10 +9,6 @@ import uncore.agents._
 case object ExportGroundTestStatus extends Field[Boolean]
 
 class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
-  override val io = new CoreplexIO {
-    // Need to export this for FPGA testing, but not for simulator
-    val status = if (p(ExportGroundTestStatus)) Some(new GroundTestStatus) else None
-  }
 
   // Not using the debug 
   io.debug.req.ready := Bool(false)
@@ -39,7 +35,9 @@ class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topPara
   mem_ic.io.in <> test.io.mem
   io.mem <> mem_ic.io.out
 
-  io.status.map { status =>
+  if (p(ExportGroundTestStatus)) {
+    val status = io.extra.asInstanceOf[GroundTestStatus]
+
     val s_running :: s_finished :: s_errored :: s_timeout :: Nil = Enum(Bits(), 4)
     val state = Reg(init = s_running)
     val error_code = Reg(status.error.bits)

coreplex/src/main/scala/TestConfigs.scala

@@ -0,0 +1,246 @@
+package coreplex
+
+import Chisel._
+import groundtest._
+import rocket._
+import uncore.tilelink._
+import uncore.coherence._
+import uncore.agents._
+import uncore.devices.NTiles
+import uncore.unittests._
+import junctions._
+import junctions.unittests._
+import scala.collection.mutable.LinkedHashSet
+import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import scala.math.max
+import ConfigUtils._
+
+class WithGroundTest extends Config(
+  (pname, site, here) => pname match {
+    case TLKey("L1toL2") => {
+      val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
+      TileLinkParameters(
+        coherencePolicy = (
+          if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
+          else new MESICoherence(site(L2DirectoryRepresentation))),
+        nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
+        nCachingClients = site(NCachedTileLinkPorts),
+        nCachelessClients = site(NUncachedTileLinkPorts),
+        maxClientXacts = ((site(NMSHRs) + 1) +:
+                           site(GroundTestKey).map(_.maxXacts))
+                             .reduce(max(_, _)),
+        maxClientsPerPort = 1,
+        maxManagerXacts = site(NAcquireTransactors) + 2,
+        dataBeats = 8,
+        dataBits = site(CacheBlockBytes)*8)
+    }
+    case BuildTiles => {
+      val groundtest = if (site(XLen) == 64)
+        DefaultTestSuites.groundtest64
+      else
+        DefaultTestSuites.groundtest32
+      TestGeneration.addSuite(groundtest("p"))
+      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
+      (0 until site(NTiles)).map { i =>
+        val tileSettings = site(GroundTestKey)(i)
+        (r: Bool, p: Parameters) => {
+          Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
+            case TLId => "L1toL2"
+            case GroundTestId => i
+            case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
+            case NUncachedTileLinkPorts => tileSettings.uncached
+            case RoccNCSRs => tileSettings.csrs
+          })))
+        }
+      }
+    }
+    case UseFPU => false
+    case UseAtomics => false
+    case UseCompressed => false
+    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
+    case _ => throw new CDEMatchError
+  })
+
+class WithComparator extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(uncached = site(ComparatorKey).targets.size)
+    }
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new ComparatorCore()(p))
+    case ComparatorKey => ComparatorParameters(
+      targets    = Seq("mem", "io:ext:testram").map(name =>
+                    site(GlobalAddrMap)(name).start.longValue),
+      width      = 8,
+      operations = 1000,
+      atomics    = site(UseAtomics),
+      prefetches = site("COMPARATOR_PREFETCHES"))
+    case UseFPU => false
+    case UseAtomics => false
+    case "COMPARATOR_PREFETCHES" => false
+    case _ => throw new CDEMatchError
+  })
+
+class WithAtomics extends Config(
+  (pname, site, here) => pname match {
+    case UseAtomics => true
+    case _ => throw new CDEMatchError
+  })
+
+class WithPrefetches extends Config(
+  (pname, site, here) => pname match {
+    case "COMPARATOR_PREFETCHES" => true
+    case _ => throw new CDEMatchError
+  })
+
+class WithMemtest extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(1, 1)
+    }
+    case GeneratorKey => GeneratorParameters(
+      maxRequests = 128,
+      startAddress = site(GlobalAddrMap)("mem").start)
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new GeneratorTest()(p))
+    case _ => throw new CDEMatchError
+  })
+
+class WithNGenerators(nUncached: Int, nCached: Int) extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(nUncached, nCached)
+    }
+    case _ => throw new CDEMatchError
+  })
+
+class WithCacheFillTest extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(uncached = 1)
+    }
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new CacheFillTest()(p))
+    case _ => throw new CDEMatchError
+  },
+  knobValues = {
+    case "L2_WAYS" => 4
+    case "L2_CAPACITY_IN_KB" => 4
+    case _ => throw new CDEMatchError
+  })
+
+class WithBroadcastRegressionTest extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(1, 1, maxXacts = 3)
+    }
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new RegressionTest()(p))
+    case GroundTestRegressions =>
+      (p: Parameters) => RegressionTests.broadcastRegressions(p)
+    case _ => throw new CDEMatchError
+  })
+
+class WithCacheRegressionTest extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(1, 1, maxXacts = 5)
+    }
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new RegressionTest()(p))
+    case GroundTestRegressions =>
+      (p: Parameters) => RegressionTests.cacheRegressions(p)
+    case _ => throw new CDEMatchError
+  })
+
+class WithNastiConverterTest extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(uncached = 1)
+    }
+    case GeneratorKey => GeneratorParameters(
+      maxRequests = 128,
+      startAddress = site(GlobalAddrMap)("mem").start)
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new NastiConverterTest()(p))
+    case _ => throw new CDEMatchError
+  })
+
+class WithTraceGen extends Config(
+  topDefinitions = (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(uncached = 1, cached = 1)
+    }
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new GroundTestTraceGenerator()(p))
+    case GeneratorKey => GeneratorParameters(
+      maxRequests = 256,
+      startAddress = 0)
+    case AddressBag => {
+      val nSets = 32 // L2 NSets
+      val nWays = 1
+      val blockOffset = site(CacheBlockOffsetBits)
+      val baseAddr = site(GlobalAddrMap)("mem").start
+      val nBeats = site(MIFDataBeats)
+      List.tabulate(4 * nWays) { i =>
+        Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
+      }.flatten.map(addr => baseAddr + BigInt(addr))
+    }
+    case UseAtomics => true
+    case _ => throw new CDEMatchError
+  },
+  knobValues = {
+    case "L1D_SETS" => 16
+    case "L1D_WAYS" => 1
+  })
+
+class WithPCIeMockupTest extends Config(
+  (pname, site, here) => pname match {
+    case NTiles => 2
+    case GroundTestKey => Seq(
+      GroundTestTileSettings(1, 1),
+      GroundTestTileSettings(1))
+    case GeneratorKey => GeneratorParameters(
+      maxRequests = 128,
+      startAddress = site(GlobalAddrMap)("mem").start)
+    case BuildGroundTest =>
+      (p: Parameters) => {
+        val id = p(GroundTestId)
+        if (id == 0) Module(new GeneratorTest()(p))
+        else Module(new NastiConverterTest()(p))
+      }
+    case _ => throw new CDEMatchError
+  })
+
+class WithDirectMemtest extends Config(
+  (pname, site, here) => {
+    val nGens = 8
+    pname match {
+      case GroundTestKey => Seq(GroundTestTileSettings(uncached = nGens))
+      case GeneratorKey => GeneratorParameters(
+        maxRequests = 1024,
+        startAddress = 0)
+      case BuildGroundTest =>
+        (p: Parameters) => Module(new GeneratorTest()(p))
+      case _ => throw new CDEMatchError
+    }
+  })
+
+class WithDirectComparator extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestKey => Seq.fill(site(NTiles)) {
+      GroundTestTileSettings(uncached = site(ComparatorKey).targets.size)
+    }
+    case BuildGroundTest =>
+      (p: Parameters) => Module(new ComparatorCore()(p))
+    case ComparatorKey => ComparatorParameters(
+      targets    = Seq(0L, 0x100L),
+      width      = 8,
+      operations = 1000,
+      atomics    = site(UseAtomics),
+      prefetches = site("COMPARATOR_PREFETCHES"))
+    case UseFPU => false
+    case UseAtomics => false
+    case "COMPARATOR_PREFETCHES" => false
+    case _ => throw new CDEMatchError
+  })

coreplex/src/main/scala/Testing.scala

@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package rocketchip
+package coreplex
 
 import Chisel._
 import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
@@ -184,56 +184,3 @@ object DefaultTestSuites {
          "bb","bc","bf","bh","bj","bk","bm","bo","br","bs","ce","cf","cg","ci","ck","cl",
          "cm","cs","cv","cy","dc","df","dm","do","dr","ds","du","dv").map(_+"_matmul")): _*))
 }
-
-object TestGenerator extends App {
-  val projectName = args(0)
-  val topModuleName = args(1)
-  val configClassName = args(2)
-
-  val aggregateConfigs = configClassName.split('_')
-
-  val finalConfig = aggregateConfigs.foldRight(new Config()) { case (currentConfigName, finalConfig) =>
-    val currentConfig = try {
-      Class.forName(s"$projectName.$currentConfigName").newInstance.asInstanceOf[Config]
-    } catch {
-      case e: java.lang.ClassNotFoundException =>
-        throwException("Unable to find part \"" + currentConfigName +
-          "\" of configClassName \"" + configClassName +
-          "\", did you misspell it?", e)
-    }
-    currentConfig ++ finalConfig
-  }
-  val world = finalConfig.toInstance
-
-  val paramsFromConfig: Parameters = Parameters.root(world)
-
-  val gen = () => 
-    Class.forName(s"$projectName.$topModuleName")
-      .getConstructor(classOf[cde.Parameters])
-      .newInstance(paramsFromConfig)
-      .asInstanceOf[Module]
-
-  chiselMain.run(args.drop(3), gen)
-  //Driver.elaborate(gen, configName = configClassName)
-
-  TestGeneration.addSuite(new RegressionTestSuite(paramsFromConfig(RegressionTestNames)))
-
-  TestGeneration.generateMakefrag(topModuleName, configClassName)
-  TestBenchGeneration.generateVerilogFragment(
-    topModuleName, configClassName, paramsFromConfig)
-  TestBenchGeneration.generateCPPFragment(
-    topModuleName, configClassName, paramsFromConfig)
-
-  val pdFile = TestGeneration.createOutputFile(s"$topModuleName.$configClassName.prm")
-  pdFile.write(ParameterDump.getDump)
-  pdFile.close
-  val v = TestGeneration.createOutputFile(configClassName + ".knb")
-  v.write(world.getKnobs)
-  v.close
-  val d = new java.io.FileOutputStream(Driver.targetDir + "/" + configClassName + ".cfg")
-  d.write(paramsFromConfig(ConfigString))
-  d.close
-  val w = TestGeneration.createOutputFile(configClassName + ".cst")
-  w.write(world.getConstraints)
-  w.close
-}

coreplex/src/main/scala/UnitTest.scala

@@ -1,4 +1,4 @@
-package rocketchip
+package coreplex
 
 import Chisel._
 import junctions.unittests.UnitTestSuite

project/build.scala

@@ -23,7 +23,8 @@ object BuildSettings extends Build {
   lazy val uncore     = project.dependsOn(junctions)
   lazy val rocket     = project.dependsOn(hardfloat, uncore)
   lazy val groundtest = project.dependsOn(rocket)
-  lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(groundtest)
+  lazy val coreplex   = project.dependsOn(groundtest)
+  lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(coreplex)
 
   lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
   lazy val make = inputKey[Unit]("trigger backend-specific makefile command")

src/main/scala/Configs.scala

@@ -4,27 +4,18 @@ package rocketchip
 
 import Chisel._
 import junctions._
-import uncore.tilelink._
+import rocket._
-import uncore.coherence._
 import uncore.agents._
+import uncore.tilelink._
 import uncore.devices._
 import uncore.converters._
-import rocket._
+import coreplex._
-import rocket.Util._
-import groundtest._
 import scala.math.max
 import scala.collection.mutable.{LinkedHashSet, ListBuffer}
 import DefaultTestSuites._
 import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
 
-object ConfigUtils {
+class BasePlatformConfig extends Config (
-  def max_int(values: Int*): Int = {
-    values.reduce((a, b) => max(a, b))
-  }
-}
-import ConfigUtils._
-
-class BaseConfig extends Config (
   topDefinitions = { (pname,site,here) => 
     type PF = PartialFunction[Any,Any]
     def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
@@ -116,14 +107,6 @@ class BaseConfig extends Config (
     lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
     pname match {
       //Memory Parameters
-      case PAddrBits => 32
-      case PgIdxBits => 12
-      case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
-      case PgLevelBits => site(PgIdxBits) - log2Up(site(XLen)/8)
-      case VPNBits => site(PgLevels) * site(PgLevelBits)
-      case PPNBits => site(PAddrBits) - site(PgIdxBits)
-      case VAddrBits => site(VPNBits) + site(PgIdxBits)
-      case ASIdBits => 7
       case MIFTagBits => Dump("MIF_TAG_BITS", 5)
       case MIFDataBits => Dump("MIF_DATA_BITS", 64)
       case MIFAddrBits => Dump("MIF_ADDR_BITS",
@@ -136,107 +119,9 @@ class BaseConfig extends Config (
           addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
           idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
       }
-      //Params used by all caches
-      case NSets => findBy(CacheName)
-      case NWays => findBy(CacheName)
-      case RowBits => findBy(CacheName)
-      case NTLBEntries => findBy(CacheName)
-      case CacheIdBits => findBy(CacheName)
-      case SplitMetadata => findBy(CacheName)
-      case "L1I" => {
-        case NSets => Knob("L1I_SETS") //64
-        case NWays => Knob("L1I_WAYS") //4
-        case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
-        case NTLBEntries => 8
-        case CacheIdBits => 0
-        case SplitMetadata => false
-      }:PF
-      case "L1D" => {
-        case NSets => Knob("L1D_SETS") //64
-        case NWays => Knob("L1D_WAYS") //4
-        case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
-        case NTLBEntries => 8
-        case CacheIdBits => 0
-        case SplitMetadata => false
-      }:PF
-      case ECCCode => None
-      case Replacer => () => new RandomReplacement(site(NWays))
-      case AmoAluOperandBits => site(XLen)
-      //L1InstCache
-      case BtbKey => BtbParameters()
-      //L1DataCache
-      case WordBits => site(XLen)
-      case StoreDataQueueDepth => 17
-      case ReplayQueueDepth => 16
-      case NMSHRs => Knob("L1D_MSHRS")
-      case LRSCCycles => 32 
-      //L2 Memory System Params
-      case NAcquireTransactors => 7
-      case L2StoreDataQueueDepth => 1
-      case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
-      case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
-        Module(new L2BroadcastHub()(p.alterPartial({
-          case InnerTLId => "L1toL2"
-          case OuterTLId => "L2toMC" })))
-      case NCachedTileLinkPorts => 1
-      case NUncachedTileLinkPorts => 1
-      //Tile Constants
-      case BuildTiles => {
-        val (rvi, rvu) =
-          if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
-          else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
-        TestGeneration.addSuites(rvi.map(_("p")))
-        TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)
-        List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
-          Module(new RocketTile(resetSignal = r)(p.alterPartial({
-            case TLId => "L1toL2"
-            case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)
-          })))
-        }
-      }
-      case BuildRoCC => Nil
       case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
-      case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
-      case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
-      case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
-      //Rocket Core Constants
-      case FetchWidth => if (site(UseCompressed)) 2 else 1
-      case RetireWidth => 1
-      case UseVM => true
-      case UseUser => true
-      case UseDebug => true
-      case AsyncDebugBus => false
-      case NBreakpoints => 1
-      case UsePerfCounters => true
-      case FastLoadWord => true
-      case FastLoadByte => false
-      case MulUnroll => 8
-      case DivEarlyOut => true
-      case XLen => 64
-      case UseFPU => {
-        val env = if(site(UseVM)) List("p","v") else List("p")
-        TestGeneration.addSuite(rv32udBenchmarks)
-        if(site(FDivSqrt)) {
-          TestGeneration.addSuites(env.map(rv64uf))
-          TestGeneration.addSuites(env.map(rv64ud))
-        } else {
-          TestGeneration.addSuites(env.map(rv64ufNoDiv))
-          TestGeneration.addSuites(env.map(rv64udNoDiv))
-        }
-        true
-      }
-      case UseAtomics => {
-        val env = if(site(UseVM)) List("p","v") else List("p")
-        TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
-        true
-      }
-      case UseCompressed => {
-        val env = if(site(UseVM)) List("p","v") else List("p")
-        TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc))
-        true
-      }
       case NExtInterrupts => 2
+      case AsyncDebugBus => false
       case AsyncMMIOChannels => false
       case ExtraDevices => Nil
       case ExtraTopPorts => (p: Parameters) => new Bundle
@@ -248,22 +133,9 @@ class BaseConfig extends Config (
       case AsyncBusChannels => false
       case NExtBusAXIChannels => 0
       case ExportBusPort => site(NExtBusAXIChannels) > 0
-      case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
+      case ConnectExtraPorts =>
-      case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
+        (out: Bundle, in: Bundle, p: Parameters) => out <> in
-      case FDivSqrt => true
+
-      case SFMALatency => 2
-      case DFMALatency => 3
-      case CoreInstBits => if (site(UseCompressed)) 16 else 32
-      case CoreDataBits => site(XLen)
-      case NCustomMRWCSRs => 0
-      case ResetVector => BigInt(0x1000)
-      case MtvecInit => BigInt(0x1010)
-      case MtvecWritable => true
-      //Uncore Paramters
-      case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
-      case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
-      case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
-                             log2Up(site(TLKey(site(TLId))).nClients)
       case HastiId => "Ext"
       case HastiKey("TL") =>
         HastiParameters(
@@ -273,232 +145,21 @@ class BaseConfig extends Config (
         HastiParameters(
           addrBits = site(PAddrBits),
           dataBits = site(XLen))
-      case TLKey("L1toL2") => {
-        val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
-        TileLinkParameters(
-          coherencePolicy = (
-            if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
-            else new MESICoherence(site(L2DirectoryRepresentation))),
-          nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
-          nCachingClients = site(NCachedTileLinkPorts),
-          nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
-          maxClientXacts = max_int(
-              // L1 cache
-              site(NMSHRs) + 1 /* IOMSHR */,
-              // RoCC
-              if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
-          maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
-          maxManagerXacts = site(NAcquireTransactors) + 2,
-          dataBeats = innerDataBeats,
-          dataBits = site(CacheBlockBytes)*8)
-      }
-      case TLKey("L2toMC") => 
-        TileLinkParameters(
-          coherencePolicy = new MEICoherence(
-            new NullRepresentation(site(NBanksPerMemoryChannel))),
-          nManagers = 1,
-          nCachingClients = site(NBanksPerMemoryChannel),
-          nCachelessClients = 0,
-          maxClientXacts = 1,
-          maxClientsPerPort = site(NAcquireTransactors) + 2,
-          maxManagerXacts = 1,
-          dataBeats = innerDataBeats,
-          dataBits = site(CacheBlockBytes)*8)
-      case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
-        maxClientXacts = site(NAcquireTransactors) + 2,
-        maxClientsPerPort = site(NBanksPerMemoryChannel),
-        dataBeats = site(MIFDataBeats))
-      case TLKey("L2toMMIO") => {
-        TileLinkParameters(
-          coherencePolicy = new MICoherence(
-            new NullRepresentation(site(NBanksPerMemoryChannel))),
-          nManagers = globalAddrMap.subMap("io").numSlaves,
-          nCachingClients = 0,
-          nCachelessClients = 1,
-          maxClientXacts = 4,
-          maxClientsPerPort = 1,
-          maxManagerXacts = 1,
-          dataBeats = innerDataBeats,
-          dataBits = site(CacheBlockBytes) * 8)
-      }
-      case BootROMFile => "./bootrom/bootrom.img"
-      case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
-      case NTiles => Knob("NTILES")
       case AsyncMemChannels => false
       case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
       case TMemoryChannels => BusType.AXI
-      case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
-      case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
-      case BankIdLSB => 0
-      case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
-      case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
       case ConfigString => makeConfigString()
       case GlobalAddrMap => globalAddrMap
-      case EnableL2Logging => false
-      case ExportGroundTestStatus => false
-      case RegressionTestNames => LinkedHashSet(
-        "rv64ud-v-fcvt",
-        "rv64ud-p-fdiv",
-        "rv64ud-v-fadd",
-        "rv64uf-v-fadd",
-        "rv64um-v-mul",
-        "rv64mi-p-breakpoint",
-        "rv64uc-v-rvc",
-        "rv64ud-v-structural",
-        "rv64si-p-wfi",
-        "rv64um-v-divw",
-        "rv64ua-v-lrsc",
-        "rv64ui-v-fence_i",
-        "rv64ud-v-fcvt_w",
-        "rv64uf-v-fmin",
-        "rv64ui-v-sb",
-        "rv64ua-v-amomax_d",
-        "rv64ud-v-move",
-        "rv64ud-v-fclass",
-        "rv64ua-v-amoand_d",
-        "rv64ua-v-amoxor_d",
-        "rv64si-p-sbreak",
-        "rv64ud-v-fmadd",
-        "rv64uf-v-ldst",
-        "rv64um-v-mulh",
-        "rv64si-p-dirty")
       case _ => throw new CDEMatchError
-  }},
+  }})
-  knobValues = {
+
-    case "NTILES" => 1
+class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
-    case "NBANKS_PER_MEM_CHANNEL" => 1
-    case "L1D_MSHRS" => 2
-    case "L1D_SETS" => 64
-    case "L1D_WAYS" => 4
-    case "L1I_SETS" => 64
-    case "L1I_WAYS" => 4
-    case _ => throw new CDEMatchError
-  }
-)
 class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
 
-class WithNCores(n: Int) extends Config(
-  knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
-
-class WithNBanksPerMemChannel(n: Int) extends Config(
-  knobValues = {
-    case "NBANKS_PER_MEM_CHANNEL" => n;
-    case _ => throw new CDEMatchError
-  })
-
-class WithNMemoryChannels(n: Int) extends Config(
-  (pname,site,here) => pname match {
-    case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
-    case _ => throw new CDEMatchError
-  }
-)
-
-class WithL2Cache extends Config(
-  (pname,site,here) => pname match {
-    case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
-    case "L2Bank" => {
-      case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
-                        site(CacheBlockBytes)) /
-                          (site(NBanksPerMemoryChannel)*site(NMemoryChannels))) /
-                            site(NWays)
-      case NWays => Knob("L2_WAYS")
-      case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
-      case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
-      case SplitMetadata => Knob("L2_SPLIT_METADATA")
-    }: PartialFunction[Any,Any] 
-    case NAcquireTransactors => 2
-    case NSecondaryMisses => 4
-    case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
-    case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
-      Module(new L2HellaCacheBank()(p.alterPartial({
-        case CacheId => id
-        case CacheName => "L2Bank"
-        case InnerTLId => "L1toL2"
-        case OuterTLId => "L2toMC"})))
-    case L2Replacer => () => new SeqRandom(site(NWays))
-    case _ => throw new CDEMatchError
-  },
-  knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError }
-)
-
-class WithBufferlessBroadcastHub extends Config(
-  (pname, site, here) => pname match {
-    case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
-      Module(new BufferlessBroadcastHub()(p.alterPartial({
-        case InnerTLId => "L1toL2"
-        case OuterTLId => "L2toMC" })))
-  })
-
-/**
- * WARNING!!! IGNORE AT YOUR OWN PERIL!!!
- *
- * There is a very restrictive set of conditions under which the stateless
- * bridge will function properly. There can only be a single tile. This tile
- * MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
- * uncached channel capable of writes (i.e. a RoCC accelerator).
- *
- * This is because the stateless bridge CANNOT generate probes, so if your
- * system depends on coherence between channels in any way,
- * DO NOT use this configuration.
- */
-class WithStatelessBridge extends Config (
-  topDefinitions = (pname, site, here) => pname match {
-    case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
-      Module(new ManagerToClientStatelessBridge()(p.alterPartial({
-        case InnerTLId => "L1toL2"
-        case OuterTLId => "L2toMC" })))
-  },
-  knobValues = {
-    case "L1D_MSHRS" => 0
-    case _ => throw new CDEMatchError
-  }
-)
-
-class WithPLRU extends Config(
-  (pname, site, here) => pname match {
-    case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
-    case _ => throw new CDEMatchError
-  })
-
-class WithL2Capacity(size_kb: Int) extends Config(
-  knobValues = {
-    case "L2_CAPACITY_IN_KB" => size_kb
-    case _ => throw new CDEMatchError
-  })
-
-class WithNL2Ways(n: Int) extends Config(
-  knobValues = {
-    case "L2_WAYS" => n
-    case _ => throw new CDEMatchError
-  })
-
 class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
-class DefaultL2FPGAConfig extends Config(
-  new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
-
 class DefaultBufferlessConfig extends Config(
   new WithBufferlessBroadcastHub ++ new BaseConfig)
 
-class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
-
-class WithRV32 extends Config(
-  (pname,site,here) => pname match {
-    case XLen => 32
-    case UseVM => false
-    case UseUser => false
-    case UseAtomics => false
-    case UseFPU => false
-    case RegressionTestNames => LinkedHashSet(
-      "rv32mi-p-ma_addr",
-      "rv32mi-p-csr",
-      "rv32ui-p-sh",
-      "rv32ui-p-lh",
-      "rv32mi-p-sbreak",
-      "rv32ui-p-sll")
-    case _ => throw new CDEMatchError
-  }
-)
-
 class FPGAConfig extends Config (
   (pname,site,here) => pname match {
     case NAcquireTransactors => 4
@@ -507,9 +168,15 @@ class FPGAConfig extends Config (
   }
 )
 
-class WithBlockingL1 extends Config (
+class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
-  knobValues = {
+class DefaultL2FPGAConfig extends Config(
-    case "L1D_MSHRS" => 0
+  new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
+
+class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
+
+class WithNMemoryChannels(n: Int) extends Config(
+  (pname,site,here) => pname match {
+    case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
     case _ => throw new CDEMatchError
   }
 )
@@ -526,30 +193,6 @@ class WithTL extends Config(
     case NExtMMIOTLChannels  => 1
   })
 
-class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
-
-class WithSmallCores extends Config (
-    topDefinitions = { (pname,site,here) => pname match {
-      case UseFPU => false
-      case MulUnroll => 1
-      case DivEarlyOut => false  
-      case NTLBEntries => 4
-      case BtbKey => BtbParameters(nEntries = 0)
-      case StoreDataQueueDepth => 2
-      case ReplayQueueDepth => 2
-      case NAcquireTransactors => 2
-      case _ => throw new CDEMatchError
-    }},
-  knobValues = {
-    case "L1D_SETS" => 64
-    case "L1D_WAYS" => 1
-    case "L1I_SETS" => 64
-    case "L1I_WAYS" => 1
-    case "L1D_MSHRS" => 0
-    case _ => throw new CDEMatchError
-  }
-)
-
 class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
 class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
 class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultSmallConfig)
@@ -570,24 +213,6 @@ class DualChannelDualBankL2Config extends Config(
   new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
   new WithL2Cache ++ new BaseConfig)
 
-class WithRoccExample extends Config(
-  (pname, site, here) => pname match {
-    case BuildRoCC => Seq(
-      RoccParameters(
-        opcodes = OpcodeSet.custom0,
-        generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
-      RoccParameters(
-        opcodes = OpcodeSet.custom1,
-        generator = (p: Parameters) => Module(new TranslatorExample()(p)),
-        nPTWPorts = 1),
-      RoccParameters(
-        opcodes = OpcodeSet.custom2,
-        generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
-
-    case RoccMaxTaggedMemXacts => 1
-    case _ => throw new CDEMatchError
-  })
-
 class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
 
 class WithMIFDataBits(n: Int) extends Config(
@@ -611,7 +236,6 @@ class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ ne
 
 class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
 
-class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
 class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
 
 class DualCoreConfig extends Config(

src/main/scala/Generator.scala

@@ -0,0 +1,61 @@
+// See LICENSE for license details.
+
+package rocketchip
+
+import Chisel._
+import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
+import cde.{Parameters, ParameterDump, Config, Field, CDEMatchError}
+import coreplex._
+
+object TestGenerator extends App {
+  val projectName = args(0)
+  val topModuleName = args(1)
+  val configClassName = args(2)
+
+  val aggregateConfigs = configClassName.split('_')
+
+  val finalConfig = aggregateConfigs.foldRight(new Config()) { case (currentConfigName, finalConfig) =>
+    val currentConfig = try {
+      Class.forName(s"$projectName.$currentConfigName").newInstance.asInstanceOf[Config]
+    } catch {
+      case e: java.lang.ClassNotFoundException =>
+        throwException("Unable to find part \"" + currentConfigName +
+          "\" of configClassName \"" + configClassName +
+          "\", did you misspell it?", e)
+    }
+    currentConfig ++ finalConfig
+  }
+  val world = finalConfig.toInstance
+
+  val paramsFromConfig: Parameters = Parameters.root(world)
+
+  val gen = () => 
+    Class.forName(s"$projectName.$topModuleName")
+      .getConstructor(classOf[cde.Parameters])
+      .newInstance(paramsFromConfig)
+      .asInstanceOf[Module]
+
+  chiselMain.run(args.drop(3), gen)
+  //Driver.elaborate(gen, configName = configClassName)
+
+  TestGeneration.addSuite(new RegressionTestSuite(paramsFromConfig(RegressionTestNames)))
+
+  TestGeneration.generateMakefrag(topModuleName, configClassName)
+  TestBenchGeneration.generateVerilogFragment(
+    topModuleName, configClassName, paramsFromConfig)
+  TestBenchGeneration.generateCPPFragment(
+    topModuleName, configClassName, paramsFromConfig)
+
+  val pdFile = TestGeneration.createOutputFile(s"$topModuleName.$configClassName.prm")
+  pdFile.write(ParameterDump.getDump)
+  pdFile.close
+  val v = TestGeneration.createOutputFile(configClassName + ".knb")
+  v.write(world.getKnobs)
+  v.close
+  val d = new java.io.FileOutputStream(Driver.targetDir + "/" + configClassName + ".cfg")
+  d.write(paramsFromConfig(ConfigString))
+  d.close
+  val w = TestGeneration.createOutputFile(configClassName + ".cst")
+  w.write(world.getConstraints)
+  w.close
+}

src/main/scala/RocketChip.scala

@@ -10,6 +10,7 @@ import uncore.devices._
 import uncore.util._
 import uncore.converters._
 import rocket._
+import coreplex._
 
 /** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
 
@@ -24,8 +25,6 @@ object BusType {
 
 /** Memory channel controls */
 case object TMemoryChannels extends Field[BusType.EnumVal]
-/** Number of outstanding memory requests */
-case object NOutstandingMemReqsPerChannel extends Field[Int]
 /** External MMIO controls */
 case object NExtMMIOAXIChannels extends Field[Int]
 case object NExtMMIOAHBChannels extends Field[Int]
@@ -37,9 +36,12 @@ case object AsyncBusChannels extends Field[Boolean]
 case object AsyncDebugBus extends Field[Boolean]
 case object AsyncMemChannels extends Field[Boolean]
 case object AsyncMMIOChannels extends Field[Boolean]
-
 /** External address map settings */
 case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
+/** Function for building Coreplex */
+case object BuildCoreplex extends Field[Parameters => Coreplex]
+/** Function for connecting coreplex extra ports to top-level extra ports */
+case object ConnectExtraPorts extends Field[(Bundle, Bundle, Parameters) => Unit]
 
 /** Utility trait for quick access to some relevant parameters */
 trait HasTopLevelParameters {
@@ -162,6 +164,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
     else io.bus_axi)
 
   io.extra <> periphery.io.extra
+  p(ConnectExtraPorts)(io.extra, coreplex.io.extra, p)
 }
 
 class Periphery(implicit val p: Parameters) extends Module

src/main/scala/TestBench.scala

@@ -5,6 +5,7 @@ package rocketchip
 import Chisel._
 import cde.Parameters
 import uncore.devices.{DbBusConsts, DMKey}
+import coreplex._
 
 object TestBenchGeneration {
   def generateVerilogFragment(

src/main/scala/TestConfigs.scala

@@ -13,159 +13,9 @@ import junctions.unittests._
 import scala.collection.mutable.LinkedHashSet
 import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
 import scala.math.max
+import coreplex._
 import ConfigUtils._
 
-class WithGroundTest extends Config(
-  (pname, site, here) => pname match {
-    case TLKey("L1toL2") => {
-      val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
-      TileLinkParameters(
-        coherencePolicy = (
-          if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
-          else new MESICoherence(site(L2DirectoryRepresentation))),
-        nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
-        nCachingClients = site(NCachedTileLinkPorts),
-        nCachelessClients = site(NUncachedTileLinkPorts),
-        maxClientXacts = ((site(NMSHRs) + 1) +:
-                           site(GroundTestKey).map(_.maxXacts))
-                             .reduce(max(_, _)),
-        maxClientsPerPort = 1,
-        maxManagerXacts = site(NAcquireTransactors) + 2,
-        dataBeats = 8,
-        dataBits = site(CacheBlockBytes)*8)
-    }
-    case BuildTiles => {
-      val groundtest = if (site(XLen) == 64)
-        DefaultTestSuites.groundtest64
-      else
-        DefaultTestSuites.groundtest32
-      TestGeneration.addSuite(groundtest("p"))
-      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
-      (0 until site(NTiles)).map { i =>
-        val tileSettings = site(GroundTestKey)(i)
-        (r: Bool, p: Parameters) => {
-          Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
-            case TLId => "L1toL2"
-            case GroundTestId => i
-            case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
-            case NUncachedTileLinkPorts => tileSettings.uncached
-            case RoccNCSRs => tileSettings.csrs
-          })))
-        }
-      }
-    }
-    case UseFPU => false
-    case UseAtomics => false
-    case UseCompressed => false
-    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
-    case _ => throw new CDEMatchError
-  })
-
-class WithComparator extends Config(
-  (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(uncached = site(ComparatorKey).targets.size)
-    }
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new ComparatorCore()(p))
-    case ComparatorKey => ComparatorParameters(
-      targets    = Seq("mem", "io:ext:testram").map(name =>
-                    site(GlobalAddrMap)(name).start.longValue),
-      width      = 8,
-      operations = 1000,
-      atomics    = site(UseAtomics),
-      prefetches = site("COMPARATOR_PREFETCHES"))
-    case UseFPU => false
-    case UseAtomics => false
-    case "COMPARATOR_PREFETCHES" => false
-    case _ => throw new CDEMatchError
-  })
-
-class WithAtomics extends Config(
-  (pname, site, here) => pname match {
-    case UseAtomics => true
-    case _ => throw new CDEMatchError
-  })
-
-class WithPrefetches extends Config(
-  (pname, site, here) => pname match {
-    case "COMPARATOR_PREFETCHES" => true
-    case _ => throw new CDEMatchError
-  })
-
-class WithMemtest extends Config(
-  (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(1, 1)
-    }
-    case GeneratorKey => GeneratorParameters(
-      maxRequests = 128,
-      startAddress = site(GlobalAddrMap)("mem").start)
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new GeneratorTest()(p))
-    case _ => throw new CDEMatchError
-  })
-
-class WithNGenerators(nUncached: Int, nCached: Int) extends Config(
-  (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(nUncached, nCached)
-    }
-    case _ => throw new CDEMatchError
-  })
-
-class WithCacheFillTest extends Config(
-  (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(uncached = 1)
-    }
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new CacheFillTest()(p))
-    case _ => throw new CDEMatchError
-  },
-  knobValues = {
-    case "L2_WAYS" => 4
-    case "L2_CAPACITY_IN_KB" => 4
-    case _ => throw new CDEMatchError
-  })
-
-class WithBroadcastRegressionTest extends Config(
-  (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(1, 1, maxXacts = 3)
-    }
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new RegressionTest()(p))
-    case GroundTestRegressions =>
-      (p: Parameters) => RegressionTests.broadcastRegressions(p)
-    case _ => throw new CDEMatchError
-  })
-
-class WithCacheRegressionTest extends Config(
-  (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(1, 1, maxXacts = 5)
-    }
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new RegressionTest()(p))
-    case GroundTestRegressions =>
-      (p: Parameters) => RegressionTests.cacheRegressions(p)
-    case _ => throw new CDEMatchError
-  })
-
-class WithNastiConverterTest extends Config(
-  (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(uncached = 1)
-    }
-    case GeneratorKey => GeneratorParameters(
-      maxRequests = 128,
-      startAddress = site(GlobalAddrMap)("mem").start)
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new NastiConverterTest()(p))
-    case _ => throw new CDEMatchError
-  })
-
 class WithUnitTest extends Config(
   (pname, site, here) => pname match {
     case BuildCoreplex => {
@@ -187,34 +37,6 @@ class WithUnitTest extends Config(
     case _ => throw new CDEMatchError
   })
 
-class WithTraceGen extends Config(
-  topDefinitions = (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(uncached = 1, cached = 1)
-    }
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new GroundTestTraceGenerator()(p))
-    case GeneratorKey => GeneratorParameters(
-      maxRequests = 256,
-      startAddress = 0)
-    case AddressBag => {
-      val nSets = 32 // L2 NSets
-      val nWays = 1
-      val blockOffset = site(CacheBlockOffsetBits)
-      val baseAddr = site(GlobalAddrMap)("mem").start
-      val nBeats = site(MIFDataBeats)
-      List.tabulate(4 * nWays) { i =>
-        Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
-      }.flatten.map(addr => baseAddr + BigInt(addr))
-    }
-    case UseAtomics => true
-    case _ => throw new CDEMatchError
-  },
-  knobValues = {
-    case "L1D_SETS" => 16
-    case "L1D_WAYS" => 1
-  })
-
 class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
 
 class ComparatorConfig extends Config(
@@ -276,71 +98,25 @@ class MIF32BitComparatorConfig extends Config(
 class MIF32BitMemtestConfig extends Config(
   new WithMIFDataBits(32) ++ new MemtestConfig)
 
-class WithPCIeMockupTest extends Config(
-  (pname, site, here) => pname match {
-    case NTiles => 2
-    case GroundTestKey => Seq(
-      GroundTestTileSettings(1, 1),
-      GroundTestTileSettings(1))
-    case GeneratorKey => GeneratorParameters(
-      maxRequests = 128,
-      startAddress = site(GlobalAddrMap)("mem").start)
-    case BuildGroundTest =>
-      (p: Parameters) => {
-        val id = p(GroundTestId)
-        if (id == 0) Module(new GeneratorTest()(p))
-        else Module(new NastiConverterTest()(p))
-      }
-    case _ => throw new CDEMatchError
-  })
-
 class PCIeMockupTestConfig extends Config(
   new WithPCIeMockupTest ++ new GroundTestConfig)
 
 class WithDirectGroundTest extends Config(
   (pname, site, here) => pname match {
+    case ExportGroundTestStatus => true
+    case BuildCoreplex => (p: Parameters) => Module(new DirectGroundTestCoreplex(p))
+    case ExtraCoreplexPorts => (p: Parameters) =>
+      if (p(ExportGroundTestStatus)) new GroundTestStatus else new Bundle
+    case ExtraTopPorts => (p: Parameters) =>
+      if (p(ExportGroundTestStatus)) new GroundTestStatus else new Bundle
     case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
       maxClientXacts = site(GroundTestKey)(0).maxXacts,
       maxClientsPerPort = site(NBanksPerMemoryChannel),
       dataBeats = site(MIFDataBeats))
-    case MIFTagBits => Dump("MIF_TAG_BITS", 2)
     case NBanksPerMemoryChannel => site(GroundTestKey)(0).uncached
     case _ => throw new CDEMatchError
   })
 
-class WithDirectMemtest extends Config(
-  (pname, site, here) => {
-    val nGens = 8
-    pname match {
-      case GroundTestKey => Seq(GroundTestTileSettings(uncached = nGens))
-      case GeneratorKey => GeneratorParameters(
-        maxRequests = 1024,
-        startAddress = 0)
-      case BuildGroundTest =>
-        (p: Parameters) => Module(new GeneratorTest()(p))
-      case _ => throw new CDEMatchError
-    }
-  })
-
-class WithDirectComparator extends Config(
-  (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) {
-      GroundTestTileSettings(uncached = site(ComparatorKey).targets.size)
-    }
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new ComparatorCore()(p))
-    case ComparatorKey => ComparatorParameters(
-      targets    = Seq(0L, 0x100L),
-      width      = 8,
-      operations = 1000,
-      atomics    = site(UseAtomics),
-      prefetches = site("COMPARATOR_PREFETCHES"))
-    case UseFPU => false
-    case UseAtomics => false
-    case "COMPARATOR_PREFETCHES" => false
-    case _ => throw new CDEMatchError
-  })
-
 class DirectGroundTestConfig extends Config(
   new WithDirectGroundTest ++ new GroundTestConfig)
 class DirectMemtestConfig extends Config(