diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index dff3590c..d8ebdc2f 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -3,7 +3,7 @@ package rocket
 import Chisel._
 import Node._
 import Constants._
-import scala.math._
+import Util._
 
 class IOTLBPTW extends Bundle {
   val req = new FIFOIO()(UFix(width = VPN_BITS))
@@ -35,16 +35,14 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
   val bitsPerLevel = VPN_BITS/levels
   require(VPN_BITS == levels * bitsPerLevel)
 
-  val count = Reg() { UFix(width = log2Up(levels)) }
   val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(5) { UFix() };
-  val state = Reg(resetVal = s_ready);
-  
-  val r_req_vpn = Reg() { Bits() }
-  val r_req_dest = Reg() { Bits() }
-  
-  val req_addr = Reg() { UFix() }
-  val r_resp_ppn = Reg() { Bits() };
-  val r_resp_perm = Reg() { Bits() };
+  val state = Reg(resetVal = s_ready)
+  val count = Reg{UFix(width = log2Up(levels))}
+
+  val r_req_vpn = Reg{Bits()}
+  val r_req_dest = Reg{Bits()}
+  val r_req_addr = Reg{UFix(width = PADDR_BITS.max(VADDR_BITS))}
+  val r_resp_perm = Reg{Bits()}
   
   val vpn_idxs = (1 until levels).map(i => r_req_vpn((levels-i)*bitsPerLevel-1, (levels-i-1)*bitsPerLevel))
   val vpn_idx = (2 until levels).foldRight(vpn_idxs(0))((i,j) => Mux(count === UFix(i-1), vpn_idxs(i-1), j))
@@ -56,20 +54,19 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
   when (arb.io.out.fire()) {
     r_req_vpn := arb.io.out.bits
     r_req_dest := arb.io.chosen
-    req_addr := Cat(io.dpath.ptbr(PADDR_BITS-1,PGIDX_BITS), arb.io.out.bits(VPN_BITS-1,VPN_BITS-bitsPerLevel), UFix(0,3))
+    r_req_addr := Cat(io.dpath.ptbr(PADDR_BITS-1,PGIDX_BITS), arb.io.out.bits(VPN_BITS-1,VPN_BITS-bitsPerLevel)) << log2Up(conf.xprlen/8)
   }
 
   when (io.mem.resp.valid) {
-    req_addr := Cat(io.mem.resp.bits.data(PADDR_BITS-1, PGIDX_BITS), vpn_idx, UFix(0,3)).toUFix
+    r_req_addr := Cat(io.mem.resp.bits.data(PADDR_BITS-1, PGIDX_BITS), vpn_idx).toUFix << log2Up(conf.xprlen/8)
     r_resp_perm := io.mem.resp.bits.data(9,4);
-    r_resp_ppn  := io.mem.resp.bits.data(PADDR_BITS-1, PGIDX_BITS);
   }
   
   io.mem.req.valid     := state === s_req
   io.mem.req.bits.phys := Bool(true)
   io.mem.req.bits.cmd  := M_XRD
   io.mem.req.bits.typ  := MT_D
-  io.mem.req.bits.addr := req_addr
+  io.mem.req.bits.addr := r_req_addr
   io.mem.req.bits.kill := Bool(false)
   
   val resp_val = state === s_done || state === s_error
@@ -77,8 +74,9 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
   
   val resp_ptd = io.mem.resp.bits.data(1,0) === Bits(1)
   val resp_pte = io.mem.resp.bits.data(1,0) === Bits(2)
- 
-  val resp_ppns = (0 until levels-1).map(i => Cat(r_resp_ppn(PPN_BITS-1, VPN_BITS-bitsPerLevel*(i+1)), r_req_vpn(VPN_BITS-1-bitsPerLevel*(i+1), 0)))
+
+  val r_resp_ppn = r_req_addr >> PGIDX_BITS
+  val resp_ppns = (0 until levels-1).map(i => Cat(r_resp_ppn >> VPN_BITS-bitsPerLevel*(i+1), r_req_vpn(VPN_BITS-1-bitsPerLevel*(i+1), 0)))
   val resp_ppn = (0 until levels-1).foldRight(r_resp_ppn)((i,j) => Mux(count === UFix(i), resp_ppns(i), j))
 
   for (i <- 0 until io.requestor.size) {