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rocketchip: switch to TL2 mmio + port PRCI

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This commit is contained in:
Wesley W. Terpstra
2016-09-14 18:09:27 -07:00
parent 91e7da4de3
commit 644f8fe974
5 changed files with 87 additions and 123 deletions
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2
src/main/scala/coreplex/Configs.scala
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@ -177,7 +177,7 @@ class BaseCoreplexConfig extends Config (
TileLinkParameters(
coherencePolicy = new MICoherence(
new NullRepresentation(site(NBanksPerMemoryChannel))),
nManagers = site(GlobalAddrMap).get.subMap("io").numSlaves,
nManagers = 1,
nCachingClients = 0,
nCachelessClients = 1,
maxClientXacts = 4,