rocketchip: switch to TL2 mmio + port PRCI

2016-09-15 21:28:56 -07:00
1 parent 91e7da4de3
commit 644f8fe974
@@ -177,7 +177,7 @@ class BaseCoreplexConfig extends Config (
        TileLinkParameters(
          coherencePolicy = new MICoherence(
            new NullRepresentation(site(NBanksPerMemoryChannel))),
-          nManagers = site(GlobalAddrMap).get.subMap("io").numSlaves,
+          nManagers = 1,
          nCachingClients = 0,
          nCachelessClients = 1,
          maxClientXacts = 4,